1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2012, Stefano Babic <sbabic@denx.de> 4 * 5 * Based on flea3.c and mx35pdk.c 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 #include <linux/errno.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/crm_regs.h> 13 #include <asm/arch/clock.h> 14 #include <asm/arch/iomux-mx35.h> 15 #include <i2c.h> 16 #include <power/pmic.h> 17 #include <fsl_pmic.h> 18 #include <mc13892.h> 19 #include <mmc.h> 20 #include <fsl_esdhc.h> 21 #include <linux/types.h> 22 #include <asm/gpio.h> 23 #include <asm/arch/sys_proto.h> 24 #include <netdev.h> 25 #include <spl.h> 26 27 #define CCM_CCMR_CONFIG 0x003F4208 28 29 #define ESDCTL_DDR2_CONFIG 0x007FFC3F 30 31 /* For MMC */ 32 #define GPIO_MMC_CD 7 33 #define GPIO_MMC_WP 8 34 35 DECLARE_GLOBAL_DATA_PTR; 36 37 int dram_init(void) 38 { 39 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, 40 PHYS_SDRAM_1_SIZE); 41 42 return 0; 43 } 44 45 static void board_setup_sdram(void) 46 { 47 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; 48 49 /* Initialize with default values both CSD0/1 */ 50 writel(0x2000, &esdc->esdctl0); 51 writel(0x2000, &esdc->esdctl1); 52 53 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, 54 13, 10, 2, 0x8080); 55 } 56 57 static void setup_iomux_fec(void) 58 { 59 static const iomux_v3_cfg_t fec_pads[] = { 60 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, 61 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, 62 MX35_PAD_FEC_RX_DV__FEC_RX_DV, 63 MX35_PAD_FEC_COL__FEC_COL, 64 MX35_PAD_FEC_RDATA0__FEC_RDATA_0, 65 MX35_PAD_FEC_TDATA0__FEC_TDATA_0, 66 MX35_PAD_FEC_TX_EN__FEC_TX_EN, 67 MX35_PAD_FEC_MDC__FEC_MDC, 68 MX35_PAD_FEC_MDIO__FEC_MDIO, 69 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, 70 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, 71 MX35_PAD_FEC_CRS__FEC_CRS, 72 MX35_PAD_FEC_RDATA1__FEC_RDATA_1, 73 MX35_PAD_FEC_TDATA1__FEC_TDATA_1, 74 MX35_PAD_FEC_RDATA2__FEC_RDATA_2, 75 MX35_PAD_FEC_TDATA2__FEC_TDATA_2, 76 MX35_PAD_FEC_RDATA3__FEC_RDATA_3, 77 MX35_PAD_FEC_TDATA3__FEC_TDATA_3, 78 }; 79 80 /* setup pins for FEC */ 81 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 82 } 83 84 int woodburn_init(void) 85 { 86 struct ccm_regs *ccm = 87 (struct ccm_regs *)IMX_CCM_BASE; 88 89 /* initialize PLL and clock configuration */ 90 writel(CCM_CCMR_CONFIG, &ccm->ccmr); 91 92 /* Set-up RAM */ 93 board_setup_sdram(); 94 95 /* enable clocks */ 96 writel(readl(&ccm->cgr0) | 97 MXC_CCM_CGR0_EMI_MASK | 98 MXC_CCM_CGR0_EDIO_MASK | 99 MXC_CCM_CGR0_EPIT1_MASK, 100 &ccm->cgr0); 101 102 writel(readl(&ccm->cgr1) | 103 MXC_CCM_CGR1_FEC_MASK | 104 MXC_CCM_CGR1_GPIO1_MASK | 105 MXC_CCM_CGR1_GPIO2_MASK | 106 MXC_CCM_CGR1_GPIO3_MASK | 107 MXC_CCM_CGR1_I2C1_MASK | 108 MXC_CCM_CGR1_I2C2_MASK | 109 MXC_CCM_CGR1_I2C3_MASK, 110 &ccm->cgr1); 111 112 /* Set-up NAND */ 113 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); 114 115 /* Set pinmux for the required peripherals */ 116 setup_iomux_fec(); 117 118 /* setup GPIO1_4 FEC_ENABLE signal */ 119 imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4); 120 gpio_direction_output(4, 1); 121 imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9); 122 gpio_direction_output(9, 1); 123 124 return 0; 125 } 126 127 #if defined(CONFIG_SPL_BUILD) 128 void board_init_f(ulong dummy) 129 { 130 /* Set the stack pointer. */ 131 asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); 132 133 /* Initialize MUX and SDRAM */ 134 woodburn_init(); 135 136 /* Clear the BSS. */ 137 memset(__bss_start, 0, __bss_end - __bss_start); 138 139 preloader_console_init(); 140 timer_init(); 141 142 board_init_r(NULL, 0); 143 } 144 145 void spl_board_init(void) 146 { 147 } 148 149 #endif 150 151 152 /* Booting from NOR in external mode */ 153 int board_early_init_f(void) 154 { 155 return woodburn_init(); 156 } 157 158 159 int board_init(void) 160 { 161 struct pmic *p; 162 u32 val; 163 int ret; 164 165 /* address of boot parameters */ 166 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 167 168 ret = pmic_init(I2C_PMIC); 169 if (ret) 170 return ret; 171 172 p = pmic_get("FSL_PMIC"); 173 174 /* 175 * Set switchers in Auto in NORMAL mode & STANDBY mode 176 * Setup the switcher mode for SW1 & SW2 177 */ 178 pmic_reg_read(p, REG_SW_4, &val); 179 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | 180 (SWMODE_MASK << SWMODE2_SHIFT))); 181 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | 182 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); 183 /* Set SWILIMB */ 184 val |= (1 << 22); 185 pmic_reg_write(p, REG_SW_4, val); 186 187 /* Setup the switcher mode for SW3 & SW4 */ 188 pmic_reg_read(p, REG_SW_5, &val); 189 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | 190 (SWMODE_MASK << SWMODE3_SHIFT)); 191 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | 192 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); 193 pmic_reg_write(p, REG_SW_5, val); 194 195 /* Set VGEN1 to 3.15V */ 196 pmic_reg_read(p, REG_SETTING_0, &val); 197 val &= ~(VGEN1_MASK); 198 val |= VGEN1_3_15; 199 pmic_reg_write(p, REG_SETTING_0, val); 200 201 pmic_reg_read(p, REG_MODE_0, &val); 202 val |= VGEN1EN; 203 pmic_reg_write(p, REG_MODE_0, val); 204 udelay(2000); 205 206 return 0; 207 } 208 209 #if defined(CONFIG_FSL_ESDHC) 210 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; 211 212 int board_mmc_init(bd_t *bis) 213 { 214 static const iomux_v3_cfg_t sdhc1_pads[] = { 215 MX35_PAD_SD1_CMD__ESDHC1_CMD, 216 MX35_PAD_SD1_CLK__ESDHC1_CLK, 217 MX35_PAD_SD1_DATA0__ESDHC1_DAT0, 218 MX35_PAD_SD1_DATA1__ESDHC1_DAT1, 219 MX35_PAD_SD1_DATA2__ESDHC1_DAT2, 220 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 221 }; 222 223 /* configure pins for SDHC1 only */ 224 imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); 225 226 /* MMC Card Detect on GPIO1_7 */ 227 imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7); 228 gpio_direction_input(GPIO_MMC_CD); 229 230 /* MMC Write Protection on GPIO1_8 */ 231 imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8); 232 gpio_direction_input(GPIO_MMC_WP); 233 234 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); 235 236 return fsl_esdhc_initialize(bis, &esdhc_cfg); 237 } 238 239 int board_mmc_getcd(struct mmc *mmc) 240 { 241 return !gpio_get_value(GPIO_MMC_CD); 242 } 243 #endif 244 245 u32 get_board_rev(void) 246 { 247 int rev = 0; 248 249 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 250 } 251