1 /* 2 * Copyright (C) 2012, Stefano Babic <sbabic@denx.de> 3 * 4 * Based on flea3.c and mx35pdk.c 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/errno.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/crm_regs.h> 14 #include <asm/arch/clock.h> 15 #include <asm/arch/iomux-mx35.h> 16 #include <i2c.h> 17 #include <power/pmic.h> 18 #include <fsl_pmic.h> 19 #include <mc13892.h> 20 #include <mmc.h> 21 #include <fsl_esdhc.h> 22 #include <linux/types.h> 23 #include <asm/gpio.h> 24 #include <asm/arch/sys_proto.h> 25 #include <netdev.h> 26 #include <spl.h> 27 28 #define CCM_CCMR_CONFIG 0x003F4208 29 30 #define ESDCTL_DDR2_CONFIG 0x007FFC3F 31 32 /* For MMC */ 33 #define GPIO_MMC_CD 7 34 #define GPIO_MMC_WP 8 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 int dram_init(void) 39 { 40 gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, 41 PHYS_SDRAM_1_SIZE); 42 43 return 0; 44 } 45 46 static void board_setup_sdram(void) 47 { 48 struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; 49 50 /* Initialize with default values both CSD0/1 */ 51 writel(0x2000, &esdc->esdctl0); 52 writel(0x2000, &esdc->esdctl1); 53 54 mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, 55 13, 10, 2, 0x8080); 56 } 57 58 static void setup_iomux_fec(void) 59 { 60 static const iomux_v3_cfg_t fec_pads[] = { 61 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK, 62 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK, 63 MX35_PAD_FEC_RX_DV__FEC_RX_DV, 64 MX35_PAD_FEC_COL__FEC_COL, 65 MX35_PAD_FEC_RDATA0__FEC_RDATA_0, 66 MX35_PAD_FEC_TDATA0__FEC_TDATA_0, 67 MX35_PAD_FEC_TX_EN__FEC_TX_EN, 68 MX35_PAD_FEC_MDC__FEC_MDC, 69 MX35_PAD_FEC_MDIO__FEC_MDIO, 70 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR, 71 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR, 72 MX35_PAD_FEC_CRS__FEC_CRS, 73 MX35_PAD_FEC_RDATA1__FEC_RDATA_1, 74 MX35_PAD_FEC_TDATA1__FEC_TDATA_1, 75 MX35_PAD_FEC_RDATA2__FEC_RDATA_2, 76 MX35_PAD_FEC_TDATA2__FEC_TDATA_2, 77 MX35_PAD_FEC_RDATA3__FEC_RDATA_3, 78 MX35_PAD_FEC_TDATA3__FEC_TDATA_3, 79 }; 80 81 /* setup pins for FEC */ 82 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads)); 83 } 84 85 int woodburn_init(void) 86 { 87 struct ccm_regs *ccm = 88 (struct ccm_regs *)IMX_CCM_BASE; 89 90 /* initialize PLL and clock configuration */ 91 writel(CCM_CCMR_CONFIG, &ccm->ccmr); 92 93 /* Set-up RAM */ 94 board_setup_sdram(); 95 96 /* enable clocks */ 97 writel(readl(&ccm->cgr0) | 98 MXC_CCM_CGR0_EMI_MASK | 99 MXC_CCM_CGR0_EDIO_MASK | 100 MXC_CCM_CGR0_EPIT1_MASK, 101 &ccm->cgr0); 102 103 writel(readl(&ccm->cgr1) | 104 MXC_CCM_CGR1_FEC_MASK | 105 MXC_CCM_CGR1_GPIO1_MASK | 106 MXC_CCM_CGR1_GPIO2_MASK | 107 MXC_CCM_CGR1_GPIO3_MASK | 108 MXC_CCM_CGR1_I2C1_MASK | 109 MXC_CCM_CGR1_I2C2_MASK | 110 MXC_CCM_CGR1_I2C3_MASK, 111 &ccm->cgr1); 112 113 /* Set-up NAND */ 114 __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); 115 116 /* Set pinmux for the required peripherals */ 117 setup_iomux_fec(); 118 119 /* setup GPIO1_4 FEC_ENABLE signal */ 120 imx_iomux_v3_setup_pad(MX35_PAD_SCKR__GPIO1_4); 121 gpio_direction_output(4, 1); 122 imx_iomux_v3_setup_pad(MX35_PAD_HCKT__GPIO1_9); 123 gpio_direction_output(9, 1); 124 125 return 0; 126 } 127 128 #if defined(CONFIG_SPL_BUILD) 129 void board_init_f(ulong dummy) 130 { 131 /* Set the stack pointer. */ 132 asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); 133 134 /* Initialize MUX and SDRAM */ 135 woodburn_init(); 136 137 /* Clear the BSS. */ 138 memset(__bss_start, 0, __bss_end - __bss_start); 139 140 preloader_console_init(); 141 timer_init(); 142 143 board_init_r(NULL, 0); 144 } 145 146 void spl_board_init(void) 147 { 148 } 149 150 #endif 151 152 153 /* Booting from NOR in external mode */ 154 int board_early_init_f(void) 155 { 156 return woodburn_init(); 157 } 158 159 160 int board_init(void) 161 { 162 struct pmic *p; 163 u32 val; 164 int ret; 165 166 /* address of boot parameters */ 167 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 168 169 ret = pmic_init(I2C_PMIC); 170 if (ret) 171 return ret; 172 173 p = pmic_get("FSL_PMIC"); 174 175 /* 176 * Set switchers in Auto in NORMAL mode & STANDBY mode 177 * Setup the switcher mode for SW1 & SW2 178 */ 179 pmic_reg_read(p, REG_SW_4, &val); 180 val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | 181 (SWMODE_MASK << SWMODE2_SHIFT))); 182 val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | 183 (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); 184 /* Set SWILIMB */ 185 val |= (1 << 22); 186 pmic_reg_write(p, REG_SW_4, val); 187 188 /* Setup the switcher mode for SW3 & SW4 */ 189 pmic_reg_read(p, REG_SW_5, &val); 190 val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | 191 (SWMODE_MASK << SWMODE3_SHIFT)); 192 val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | 193 (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); 194 pmic_reg_write(p, REG_SW_5, val); 195 196 /* Set VGEN1 to 3.15V */ 197 pmic_reg_read(p, REG_SETTING_0, &val); 198 val &= ~(VGEN1_MASK); 199 val |= VGEN1_3_15; 200 pmic_reg_write(p, REG_SETTING_0, val); 201 202 pmic_reg_read(p, REG_MODE_0, &val); 203 val |= VGEN1EN; 204 pmic_reg_write(p, REG_MODE_0, val); 205 udelay(2000); 206 207 return 0; 208 } 209 210 #if defined(CONFIG_FSL_ESDHC) 211 struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; 212 213 int board_mmc_init(bd_t *bis) 214 { 215 static const iomux_v3_cfg_t sdhc1_pads[] = { 216 MX35_PAD_SD1_CMD__ESDHC1_CMD, 217 MX35_PAD_SD1_CLK__ESDHC1_CLK, 218 MX35_PAD_SD1_DATA0__ESDHC1_DAT0, 219 MX35_PAD_SD1_DATA1__ESDHC1_DAT1, 220 MX35_PAD_SD1_DATA2__ESDHC1_DAT2, 221 MX35_PAD_SD1_DATA3__ESDHC1_DAT3, 222 }; 223 224 /* configure pins for SDHC1 only */ 225 imx_iomux_v3_setup_multiple_pads(sdhc1_pads, ARRAY_SIZE(sdhc1_pads)); 226 227 /* MMC Card Detect on GPIO1_7 */ 228 imx_iomux_v3_setup_pad(MX35_PAD_SCKT__GPIO1_7); 229 gpio_direction_input(GPIO_MMC_CD); 230 231 /* MMC Write Protection on GPIO1_8 */ 232 imx_iomux_v3_setup_pad(MX35_PAD_FST__GPIO1_8); 233 gpio_direction_input(GPIO_MMC_WP); 234 235 esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); 236 237 return fsl_esdhc_initialize(bis, &esdhc_cfg); 238 } 239 240 int board_mmc_getcd(struct mmc *mmc) 241 { 242 return !gpio_get_value(GPIO_MMC_CD); 243 } 244 #endif 245 246 u32 get_board_rev(void) 247 { 248 int rev = 0; 249 250 return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 251 } 252