1d81b27a2SStefano Babic /* 2d81b27a2SStefano Babic * Copyright (C) 2012, Stefano Babic <sbabic@denx.de> 3d81b27a2SStefano Babic * 4d81b27a2SStefano Babic * Based on flea3.c and mx35pdk.c 5d81b27a2SStefano Babic * 6d81b27a2SStefano Babic * See file CREDITS for list of people who contributed to this 7d81b27a2SStefano Babic * project. 8d81b27a2SStefano Babic * 9d81b27a2SStefano Babic * This program is free software; you can redistribute it and/or 10d81b27a2SStefano Babic * modify it under the terms of the GNU General Public License as 11d81b27a2SStefano Babic * published by the Free Software Foundation; either version 2 of 12d81b27a2SStefano Babic * the License, or (at your option) any later version. 13d81b27a2SStefano Babic * 14d81b27a2SStefano Babic * This program is distributed in the hope that it will be useful, 15d81b27a2SStefano Babic * but WITHOUT ANY WARRANTY; without even the implied warranty of 16d81b27a2SStefano Babic * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17d81b27a2SStefano Babic * GNU General Public License for more details. 18d81b27a2SStefano Babic * 19d81b27a2SStefano Babic * You should have received a copy of the GNU General Public License 20d81b27a2SStefano Babic * along with this program; if not, write to the Free Software 21d81b27a2SStefano Babic * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22d81b27a2SStefano Babic * MA 02111-1307 USA 23d81b27a2SStefano Babic */ 24d81b27a2SStefano Babic 25d81b27a2SStefano Babic #include <common.h> 26d81b27a2SStefano Babic #include <asm/io.h> 27d81b27a2SStefano Babic #include <asm/errno.h> 28d81b27a2SStefano Babic #include <asm/arch/imx-regs.h> 29d81b27a2SStefano Babic #include <asm/arch/crm_regs.h> 30d81b27a2SStefano Babic #include <asm/arch/clock.h> 31d81b27a2SStefano Babic #include <asm/arch/mx35_pins.h> 32d81b27a2SStefano Babic #include <asm/arch/iomux.h> 33d81b27a2SStefano Babic #include <i2c.h> 34*05a860c2SStefano Babic #include <power/pmic.h> 35d81b27a2SStefano Babic #include <fsl_pmic.h> 36d81b27a2SStefano Babic #include <mc13892.h> 37d81b27a2SStefano Babic #include <mmc.h> 38d81b27a2SStefano Babic #include <fsl_esdhc.h> 39d81b27a2SStefano Babic #include <linux/types.h> 40d81b27a2SStefano Babic #include <asm/gpio.h> 41d81b27a2SStefano Babic #include <asm/arch/sys_proto.h> 42d81b27a2SStefano Babic #include <netdev.h> 43d81b27a2SStefano Babic #include <spl.h> 44d81b27a2SStefano Babic 45d81b27a2SStefano Babic #define CCM_CCMR_CONFIG 0x003F4208 46d81b27a2SStefano Babic 47d81b27a2SStefano Babic #define ESDCTL_DDR2_CONFIG 0x007FFC3F 48d81b27a2SStefano Babic 49d81b27a2SStefano Babic /* For MMC */ 50d81b27a2SStefano Babic #define GPIO_MMC_CD 7 51d81b27a2SStefano Babic #define GPIO_MMC_WP 8 52d81b27a2SStefano Babic 53d81b27a2SStefano Babic DECLARE_GLOBAL_DATA_PTR; 54d81b27a2SStefano Babic 55d81b27a2SStefano Babic int dram_init(void) 56d81b27a2SStefano Babic { 57d81b27a2SStefano Babic gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, 58d81b27a2SStefano Babic PHYS_SDRAM_1_SIZE); 59d81b27a2SStefano Babic 60d81b27a2SStefano Babic return 0; 61d81b27a2SStefano Babic } 62d81b27a2SStefano Babic 63d81b27a2SStefano Babic static void board_setup_sdram(void) 64d81b27a2SStefano Babic { 65d81b27a2SStefano Babic struct esdc_regs *esdc = (struct esdc_regs *)ESDCTL_BASE_ADDR; 66d81b27a2SStefano Babic 67d81b27a2SStefano Babic /* Initialize with default values both CSD0/1 */ 68d81b27a2SStefano Babic writel(0x2000, &esdc->esdctl0); 69d81b27a2SStefano Babic writel(0x2000, &esdc->esdctl1); 70d81b27a2SStefano Babic 71d81b27a2SStefano Babic mx3_setup_sdram_bank(CSD0_BASE_ADDR, ESDCTL_DDR2_CONFIG, 72d81b27a2SStefano Babic 13, 10, 2, 0x8080); 73d81b27a2SStefano Babic } 74d81b27a2SStefano Babic 75d81b27a2SStefano Babic static void setup_iomux_fec(void) 76d81b27a2SStefano Babic { 77d81b27a2SStefano Babic /* setup pins for FEC */ 78d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_TX_CLK, MUX_CONFIG_FUNC); 79d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_RX_CLK, MUX_CONFIG_FUNC); 80d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_RX_DV, MUX_CONFIG_FUNC); 81d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_COL, MUX_CONFIG_FUNC); 82d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_RDATA0, MUX_CONFIG_FUNC); 83d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_TDATA0, MUX_CONFIG_FUNC); 84d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_TX_EN, MUX_CONFIG_FUNC); 85d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_MDC, MUX_CONFIG_FUNC); 86d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_MDIO, MUX_CONFIG_FUNC); 87d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_TX_ERR, MUX_CONFIG_FUNC); 88d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_RX_ERR, MUX_CONFIG_FUNC); 89d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_CRS, MUX_CONFIG_FUNC); 90d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_RDATA1, MUX_CONFIG_FUNC); 91d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_TDATA1, MUX_CONFIG_FUNC); 92d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_RDATA2, MUX_CONFIG_FUNC); 93d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_TDATA2, MUX_CONFIG_FUNC); 94d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_RDATA3, MUX_CONFIG_FUNC); 95d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FEC_TDATA3, MUX_CONFIG_FUNC); 96d81b27a2SStefano Babic } 97d81b27a2SStefano Babic 98d81b27a2SStefano Babic int woodburn_init(void) 99d81b27a2SStefano Babic { 100d81b27a2SStefano Babic struct ccm_regs *ccm = 101d81b27a2SStefano Babic (struct ccm_regs *)IMX_CCM_BASE; 102d81b27a2SStefano Babic 103d81b27a2SStefano Babic /* initialize PLL and clock configuration */ 104d81b27a2SStefano Babic writel(CCM_CCMR_CONFIG, &ccm->ccmr); 105d81b27a2SStefano Babic 106d81b27a2SStefano Babic /* Set-up RAM */ 107d81b27a2SStefano Babic board_setup_sdram(); 108d81b27a2SStefano Babic 109d81b27a2SStefano Babic /* enable clocks */ 110d81b27a2SStefano Babic writel(readl(&ccm->cgr0) | 111d81b27a2SStefano Babic MXC_CCM_CGR0_EMI_MASK | 112d81b27a2SStefano Babic MXC_CCM_CGR0_EDIO_MASK | 113d81b27a2SStefano Babic MXC_CCM_CGR0_EPIT1_MASK, 114d81b27a2SStefano Babic &ccm->cgr0); 115d81b27a2SStefano Babic 116d81b27a2SStefano Babic writel(readl(&ccm->cgr1) | 117d81b27a2SStefano Babic MXC_CCM_CGR1_FEC_MASK | 118d81b27a2SStefano Babic MXC_CCM_CGR1_GPIO1_MASK | 119d81b27a2SStefano Babic MXC_CCM_CGR1_GPIO2_MASK | 120d81b27a2SStefano Babic MXC_CCM_CGR1_GPIO3_MASK | 121d81b27a2SStefano Babic MXC_CCM_CGR1_I2C1_MASK | 122d81b27a2SStefano Babic MXC_CCM_CGR1_I2C2_MASK | 123d81b27a2SStefano Babic MXC_CCM_CGR1_I2C3_MASK, 124d81b27a2SStefano Babic &ccm->cgr1); 125d81b27a2SStefano Babic 126d81b27a2SStefano Babic /* Set-up NAND */ 127d81b27a2SStefano Babic __raw_writel(readl(&ccm->rcsr) | MXC_CCM_RCSR_NFC_FMS, &ccm->rcsr); 128d81b27a2SStefano Babic 129d81b27a2SStefano Babic /* Set pinmux for the required peripherals */ 130d81b27a2SStefano Babic setup_iomux_fec(); 131d81b27a2SStefano Babic 132d81b27a2SStefano Babic /* setup GPIO1_4 FEC_ENABLE signal */ 133d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SCKR, MUX_CONFIG_ALT5); 134d81b27a2SStefano Babic gpio_direction_output(4, 1); 135d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_HCKT, MUX_CONFIG_ALT5); 136d81b27a2SStefano Babic gpio_direction_output(9, 0); 137d81b27a2SStefano Babic gpio_set_value(9, 1); 138d81b27a2SStefano Babic 139d81b27a2SStefano Babic return 0; 140d81b27a2SStefano Babic } 141d81b27a2SStefano Babic 142d81b27a2SStefano Babic #if defined(CONFIG_SPL_BUILD) 143d81b27a2SStefano Babic void board_init_f(ulong dummy) 144d81b27a2SStefano Babic { 145d81b27a2SStefano Babic /* Set the stack pointer. */ 146d81b27a2SStefano Babic asm volatile("mov sp, %0\n" : : "r"(CONFIG_SPL_STACK)); 147d81b27a2SStefano Babic 148d81b27a2SStefano Babic /* Initialize MUX and SDRAM */ 149d81b27a2SStefano Babic woodburn_init(); 150d81b27a2SStefano Babic 151d81b27a2SStefano Babic /* Clear the BSS. */ 152d81b27a2SStefano Babic memset(__bss_start, 0, __bss_end__ - __bss_start); 153d81b27a2SStefano Babic 154d81b27a2SStefano Babic /* Set global data pointer. */ 155d81b27a2SStefano Babic gd = &gdata; 156d81b27a2SStefano Babic 157d81b27a2SStefano Babic preloader_console_init(); 158d81b27a2SStefano Babic timer_init(); 159d81b27a2SStefano Babic 160d81b27a2SStefano Babic board_init_r(NULL, 0); 161d81b27a2SStefano Babic } 162d81b27a2SStefano Babic 163d81b27a2SStefano Babic void spl_board_init(void) 164d81b27a2SStefano Babic { 165d81b27a2SStefano Babic } 166d81b27a2SStefano Babic 167d81b27a2SStefano Babic #endif 168d81b27a2SStefano Babic 169d81b27a2SStefano Babic 170d81b27a2SStefano Babic /* Booting from NOR in external mode */ 171d81b27a2SStefano Babic int board_early_init_f(void) 172d81b27a2SStefano Babic { 173d81b27a2SStefano Babic return woodburn_init(); 174d81b27a2SStefano Babic } 175d81b27a2SStefano Babic 176d81b27a2SStefano Babic 177d81b27a2SStefano Babic int board_init(void) 178d81b27a2SStefano Babic { 179d81b27a2SStefano Babic struct pmic *p; 180d81b27a2SStefano Babic u32 val; 181*05a860c2SStefano Babic int ret; 182d81b27a2SStefano Babic 183d81b27a2SStefano Babic /* address of boot parameters */ 184d81b27a2SStefano Babic gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; 185d81b27a2SStefano Babic 186*05a860c2SStefano Babic ret = pmic_init(I2C_PMIC); 187*05a860c2SStefano Babic if (ret) 188*05a860c2SStefano Babic return ret; 189*05a860c2SStefano Babic 190*05a860c2SStefano Babic p = pmic_get("FSL_PMIC"); 191d81b27a2SStefano Babic 192d81b27a2SStefano Babic /* 193d81b27a2SStefano Babic * Set switchers in Auto in NORMAL mode & STANDBY mode 194d81b27a2SStefano Babic * Setup the switcher mode for SW1 & SW2 195d81b27a2SStefano Babic */ 196d81b27a2SStefano Babic pmic_reg_read(p, REG_SW_4, &val); 197d81b27a2SStefano Babic val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | 198d81b27a2SStefano Babic (SWMODE_MASK << SWMODE2_SHIFT))); 199d81b27a2SStefano Babic val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | 200d81b27a2SStefano Babic (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); 201d81b27a2SStefano Babic /* Set SWILIMB */ 202d81b27a2SStefano Babic val |= (1 << 22); 203d81b27a2SStefano Babic pmic_reg_write(p, REG_SW_4, val); 204d81b27a2SStefano Babic 205d81b27a2SStefano Babic /* Setup the switcher mode for SW3 & SW4 */ 206d81b27a2SStefano Babic pmic_reg_read(p, REG_SW_5, &val); 207d81b27a2SStefano Babic val &= ~((SWMODE_MASK << SWMODE4_SHIFT) | 208d81b27a2SStefano Babic (SWMODE_MASK << SWMODE3_SHIFT)); 209d81b27a2SStefano Babic val |= (SWMODE_AUTO_AUTO << SWMODE4_SHIFT) | 210d81b27a2SStefano Babic (SWMODE_AUTO_AUTO << SWMODE3_SHIFT); 211d81b27a2SStefano Babic pmic_reg_write(p, REG_SW_5, val); 212d81b27a2SStefano Babic 213d81b27a2SStefano Babic /* Set VGEN1 to 3.15V */ 214d81b27a2SStefano Babic pmic_reg_read(p, REG_SETTING_0, &val); 215d81b27a2SStefano Babic val &= ~(VGEN1_MASK); 216d81b27a2SStefano Babic val |= VGEN1_3_15; 217d81b27a2SStefano Babic pmic_reg_write(p, REG_SETTING_0, val); 218d81b27a2SStefano Babic 219d81b27a2SStefano Babic pmic_reg_read(p, REG_MODE_0, &val); 220d81b27a2SStefano Babic val |= VGEN1EN; 221d81b27a2SStefano Babic pmic_reg_write(p, REG_MODE_0, val); 222d81b27a2SStefano Babic udelay(2000); 223d81b27a2SStefano Babic 224d81b27a2SStefano Babic return 0; 225d81b27a2SStefano Babic } 226d81b27a2SStefano Babic 227d81b27a2SStefano Babic #if defined(CONFIG_FSL_ESDHC) 228d81b27a2SStefano Babic struct fsl_esdhc_cfg esdhc_cfg = {MMC_SDHC1_BASE_ADDR}; 229d81b27a2SStefano Babic 230d81b27a2SStefano Babic int board_mmc_init(bd_t *bis) 231d81b27a2SStefano Babic { 232d81b27a2SStefano Babic /* configure pins for SDHC1 only */ 233d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SD1_CMD, MUX_CONFIG_FUNC); 234d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SD1_CLK, MUX_CONFIG_FUNC); 235d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SD1_DATA0, MUX_CONFIG_FUNC); 236d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SD1_DATA1, MUX_CONFIG_FUNC); 237d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SD1_DATA2, MUX_CONFIG_FUNC); 238d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SD1_DATA3, MUX_CONFIG_FUNC); 239d81b27a2SStefano Babic 240d81b27a2SStefano Babic /* MMC Card Detect on GPIO1_7 */ 241d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_SCKT, MUX_CONFIG_ALT5); 242d81b27a2SStefano Babic mxc_iomux_set_input(MUX_IN_GPIO1_IN_7, 0x1); 243d81b27a2SStefano Babic gpio_direction_input(GPIO_MMC_CD); 244d81b27a2SStefano Babic 245d81b27a2SStefano Babic mxc_request_iomux(MX35_PIN_FST, MUX_CONFIG_ALT5); 246d81b27a2SStefano Babic mxc_iomux_set_input(MUX_IN_GPIO1_IN_8, 0x1); 247d81b27a2SStefano Babic gpio_direction_output(GPIO_MMC_WP, 0); 248d81b27a2SStefano Babic 249d81b27a2SStefano Babic esdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK); 250d81b27a2SStefano Babic 251d81b27a2SStefano Babic return fsl_esdhc_initialize(bis, &esdhc_cfg); 252d81b27a2SStefano Babic } 253d81b27a2SStefano Babic 254d81b27a2SStefano Babic int board_mmc_getcd(struct mmc *mmc) 255d81b27a2SStefano Babic { 256d81b27a2SStefano Babic return !gpio_get_value(GPIO_MMC_CD); 257d81b27a2SStefano Babic } 258d81b27a2SStefano Babic #endif 259d81b27a2SStefano Babic 260d81b27a2SStefano Babic u32 get_board_rev(void) 261d81b27a2SStefano Babic { 262d81b27a2SStefano Babic int rev = 0; 263d81b27a2SStefano Babic 264d81b27a2SStefano Babic return (get_cpu_rev() & ~(0xF << 8)) | (rev & 0xF) << 8; 265d81b27a2SStefano Babic } 266