1 /* 2 * Copyright (C) 2016 NXP Semiconductors 3 * Author: Fabio Estevam <fabio.estevam@nxp.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <asm/arch/clock.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/mx7-pins.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/gpio.h> 13 #include <asm/mach-imx/iomux-v3.h> 14 #include <asm/mach-imx/mxc_i2c.h> 15 #include <asm/io.h> 16 #include <common.h> 17 #include <fsl_esdhc.h> 18 #include <i2c.h> 19 #include <mmc.h> 20 #include <asm/arch/crm_regs.h> 21 #include <usb.h> 22 #include <netdev.h> 23 #include <power/pmic.h> 24 #include <power/pfuze3000_pmic.h> 25 #include "../freescale/common/pfuze.h" 26 #include <asm/setup.h> 27 #include <asm/bootm.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \ 32 PAD_CTL_HYS) 33 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 34 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 35 36 #define I2C_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 37 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU100KOHM) 38 39 #ifdef CONFIG_SYS_I2C_MXC 40 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) 41 /* I2C1 for PMIC */ 42 static struct i2c_pads_info i2c_pad_info1 = { 43 .scl = { 44 .i2c_mode = MX7D_PAD_I2C1_SCL__I2C1_SCL | PC, 45 .gpio_mode = MX7D_PAD_I2C1_SCL__GPIO4_IO8 | PC, 46 .gp = IMX_GPIO_NR(4, 8), 47 }, 48 .sda = { 49 .i2c_mode = MX7D_PAD_I2C1_SDA__I2C1_SDA | PC, 50 .gpio_mode = MX7D_PAD_I2C1_SDA__GPIO4_IO9 | PC, 51 .gp = IMX_GPIO_NR(4, 9), 52 }, 53 }; 54 #endif 55 56 int dram_init(void) 57 { 58 gd->ram_size = PHYS_SDRAM_SIZE; 59 60 return 0; 61 } 62 63 static iomux_v3_cfg_t const wdog_pads[] = { 64 MX7D_PAD_GPIO1_IO00__WDOG1_WDOG_B | MUX_PAD_CTRL(NO_PAD_CTRL), 65 }; 66 67 static iomux_v3_cfg_t const uart1_pads[] = { 68 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 69 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 70 }; 71 72 static iomux_v3_cfg_t const usdhc3_pads[] = { 73 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX7D_PAD_SD3_RESET_B__SD3_RESET_B | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 }; 85 86 static void setup_iomux_uart(void) 87 { 88 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 89 }; 90 91 static struct fsl_esdhc_cfg usdhc_cfg[1] = { 92 {USDHC3_BASE_ADDR}, 93 }; 94 95 int board_mmc_getcd(struct mmc *mmc) 96 { 97 /* Assume uSDHC3 emmc is always present */ 98 return 1; 99 } 100 101 int board_mmc_init(bd_t *bis) 102 { 103 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 104 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 105 106 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 107 } 108 109 int board_early_init_f(void) 110 { 111 setup_iomux_uart(); 112 113 return 0; 114 } 115 116 #ifdef CONFIG_POWER 117 #define I2C_PMIC 0 118 static struct pmic *pfuze; 119 int power_init_board(void) 120 { 121 int ret; 122 unsigned int reg, rev_id; 123 124 ret = power_pfuze3000_init(I2C_PMIC); 125 if (ret) 126 return ret; 127 128 pfuze = pmic_get("PFUZE3000"); 129 ret = pmic_probe(pfuze); 130 if (ret) 131 return ret; 132 133 pmic_reg_read(pfuze, PFUZE3000_DEVICEID, ®); 134 pmic_reg_read(pfuze, PFUZE3000_REVID, &rev_id); 135 printf("PMIC: PFUZE3000 DEV_ID=0x%x REV_ID=0x%x\n", reg, rev_id); 136 137 /* disable Low Power Mode during standby mode */ 138 pmic_reg_write(pfuze, PFUZE3000_LDOGCTL, 0x1); 139 140 return 0; 141 } 142 #endif 143 144 int board_eth_init(bd_t *bis) 145 { 146 int ret = 0; 147 148 #ifdef CONFIG_USB_ETHER 149 ret = usb_eth_initialize(bis); 150 if (ret < 0) 151 printf("Error %d registering USB ether.\n", ret); 152 #endif 153 154 return ret; 155 } 156 157 int board_init(void) 158 { 159 /* address of boot parameters */ 160 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 161 162 #ifdef CONFIG_SYS_I2C_MXC 163 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); 164 #endif 165 166 return 0; 167 } 168 169 int checkboard(void) 170 { 171 char *mode; 172 173 if (IS_ENABLED(CONFIG_ARMV7_BOOT_SEC_DEFAULT)) 174 mode = "secure"; 175 else 176 mode = "non-secure"; 177 178 printf("Board: WARP7 in %s mode\n", mode); 179 180 return 0; 181 } 182 183 int board_usb_phy_mode(int port) 184 { 185 return USB_INIT_DEVICE; 186 } 187 188 int board_late_init(void) 189 { 190 struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; 191 #ifdef CONFIG_SERIAL_TAG 192 struct tag_serialnr serialnr; 193 char serial_string[0x20]; 194 #endif 195 196 imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); 197 198 set_wdog_reset(wdog); 199 200 /* 201 * Do not assert internal WDOG_RESET_B_DEB(controlled by bit 4), 202 * since we use PMIC_PWRON to reset the board. 203 */ 204 clrsetbits_le16(&wdog->wcr, 0, 0x10); 205 206 #ifdef CONFIG_SERIAL_TAG 207 /* Set serial# standard environment variable based on OTP settings */ 208 get_board_serial(&serialnr); 209 snprintf(serial_string, sizeof(serial_string), "WaRP7-0x%08x%08x", 210 serialnr.low, serialnr.high); 211 env_set("serial#", serial_string); 212 #endif 213 214 return 0; 215 } 216