xref: /openbmc/u-boot/board/warp/warp.c (revision d330e04d9d427a26381b59f40875af17f4c288a2)
1  /*
2   * Copyright (C) 2014, 2015 O.S. Systems Software LTDA.
3   * Copyright (C) 2014 Kynetics LLC.
4   * Copyright (C) 2014 Revolution Robotics, Inc.
5   *
6   * Author: Otavio Salvador <otavio@ossystems.com.br>
7   *
8   * SPDX-License-Identifier:	GPL-2.0+
9   */
10  
11  #include <asm/arch/clock.h>
12  #include <asm/arch/iomux.h>
13  #include <asm/arch/imx-regs.h>
14  #include <asm/arch/mx6-pins.h>
15  #include <asm/arch/sys_proto.h>
16  #include <asm/gpio.h>
17  #include <asm/mach-imx/iomux-v3.h>
18  #include <asm/mach-imx/mxc_i2c.h>
19  #include <asm/io.h>
20  #include <linux/sizes.h>
21  #include <common.h>
22  #include <watchdog.h>
23  #include <fsl_esdhc.h>
24  #include <i2c.h>
25  #include <mmc.h>
26  #include <usb.h>
27  #include <power/pmic.h>
28  #include <power/max77696_pmic.h>
29  
30  DECLARE_GLOBAL_DATA_PTR;
31  
32  #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
33  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
34  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS | \
35  	PAD_CTL_LVE)
36  
37  #define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
38  	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
39  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS | \
40  	PAD_CTL_LVE)
41  
42  #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE |		\
43  		      PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |	\
44  		      PAD_CTL_DSE_40ohm | PAD_CTL_HYS |		\
45  		      PAD_CTL_ODE | PAD_CTL_SRE_FAST)
46  
47  int dram_init(void)
48  {
49  	gd->ram_size = imx_ddr_size();
50  
51  	return 0;
52  }
53  
54  static void setup_iomux_uart(void)
55  {
56  	static iomux_v3_cfg_t const uart1_pads[] = {
57  		MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
58  		MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
59  	};
60  
61  	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
62  }
63  
64  static struct fsl_esdhc_cfg usdhc_cfg[1] = {
65  	{USDHC2_BASE_ADDR, 0, 0, 0, 1},
66  };
67  
68  int board_mmc_getcd(struct mmc *mmc)
69  {
70  	return 1;	/* Assume boot SD always present */
71  }
72  
73  int board_mmc_init(bd_t *bis)
74  {
75  	static iomux_v3_cfg_t const usdhc2_pads[] = {
76  		MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77  		MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78  		MX6_PAD_SD2_RST__USDHC2_RST | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79  		MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80  		MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81  		MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82  		MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83  		MX6_PAD_SD2_DAT4__USDHC2_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84  		MX6_PAD_SD2_DAT5__USDHC2_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
85  		MX6_PAD_SD2_DAT6__USDHC2_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
86  		MX6_PAD_SD2_DAT7__USDHC2_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
87  	};
88  
89  	imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
90  
91  	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
92  	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
93  }
94  
95  int board_usb_phy_mode(int port)
96  {
97  	return USB_INIT_DEVICE;
98  }
99  
100  /* I2C1 for PMIC */
101  #define I2C_PMIC	0
102  #define PC	MUX_PAD_CTRL(I2C_PAD_CTRL)
103  struct i2c_pads_info i2c_pad_info1 = {
104  	.sda = {
105  		.i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
106  		.gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
107  		.gp = IMX_GPIO_NR(3, 13),
108  	},
109  	.scl = {
110  		.i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
111  		.gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
112  		.gp = IMX_GPIO_NR(3, 12),
113  	},
114  };
115  
116  int power_init_board(void)
117  {
118  	struct pmic *p;
119  	int ret;
120  	unsigned int reg;
121  
122  	ret = power_max77696_init(I2C_PMIC);
123  	if (ret)
124  		return ret;
125  
126  	p = pmic_get("MAX77696");
127  	if (!p)
128  		return -EINVAL;
129  
130  	ret = pmic_reg_read(p, CID, &reg);
131  	if (ret)
132  		return ret;
133  
134  	printf("PMIC:  MAX77696 detected, rev=0x%x\n", reg);
135  
136  	return pmic_probe(p);
137  }
138  
139  int board_early_init_f(void)
140  {
141  	setup_iomux_uart();
142  	return 0;
143  }
144  
145  int board_init(void)
146  {
147  	/* address of boot parameters */
148  	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
149  
150  	setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
151  
152  	return 0;
153  }
154  
155  int board_late_init(void)
156  {
157  #ifdef CONFIG_HW_WATCHDOG
158  	hw_watchdog_init();
159  #endif
160  
161  	return 0;
162  }
163  
164  int checkboard(void)
165  {
166  	puts("Board: WaRP Board\n");
167  
168  	return 0;
169  }
170