1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * 4 * Author: Fabio Estevam <fabio.estevam@freescale.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/arch/clock.h> 10 #include <asm/arch/crm_regs.h> 11 #include <asm/arch/iomux.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/mxc_hdmi.h> 15 #include <asm/arch/sys_proto.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/iomux-v3.h> 18 #include <asm/imx-common/boot_mode.h> 19 #include <asm/io.h> 20 #include <linux/sizes.h> 21 #include <common.h> 22 #include <fsl_esdhc.h> 23 #include <ipu_pixfmt.h> 24 #include <mmc.h> 25 #include <miiphy.h> 26 #include <netdev.h> 27 #include <linux/fb.h> 28 #include <phy.h> 29 #include <input.h> 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 35 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 36 37 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 38 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 39 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 40 41 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 42 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 43 44 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) 45 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) 46 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) 47 48 int dram_init(void) 49 { 50 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; 51 52 return 0; 53 } 54 55 static iomux_v3_cfg_t const uart1_pads[] = { 56 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 57 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 58 }; 59 60 static iomux_v3_cfg_t const usdhc1_pads[] = { 61 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 62 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 63 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 64 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 /* Carrier MicroSD Card Detect */ 68 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), 69 }; 70 71 static iomux_v3_cfg_t const usdhc3_pads[] = { 72 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 /* SOM MicroSD Card Detect */ 79 MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 80 }; 81 82 static iomux_v3_cfg_t const enet_pads[] = { 83 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 84 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 85 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 86 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 87 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 88 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 89 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 90 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 91 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 92 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 93 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 94 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 95 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 96 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 97 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 98 /* AR8031 PHY Reset */ 99 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 100 }; 101 102 static void setup_iomux_uart(void) 103 { 104 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 105 } 106 107 static void setup_iomux_enet(void) 108 { 109 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 110 111 /* Reset AR8031 PHY */ 112 gpio_direction_output(ETH_PHY_RESET, 0); 113 udelay(500); 114 gpio_set_value(ETH_PHY_RESET, 1); 115 } 116 117 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 118 {USDHC3_BASE_ADDR}, 119 {USDHC1_BASE_ADDR}, 120 }; 121 122 int board_mmc_getcd(struct mmc *mmc) 123 { 124 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 125 int ret = 0; 126 127 switch (cfg->esdhc_base) { 128 case USDHC1_BASE_ADDR: 129 ret = !gpio_get_value(USDHC1_CD_GPIO); 130 break; 131 case USDHC3_BASE_ADDR: 132 ret = !gpio_get_value(USDHC3_CD_GPIO); 133 break; 134 } 135 136 return ret; 137 } 138 139 int board_mmc_init(bd_t *bis) 140 { 141 s32 status = 0; 142 u32 index = 0; 143 144 /* 145 * Following map is done: 146 * (U-boot device node) (Physical Port) 147 * mmc0 SOM MicroSD 148 * mmc1 Carrier board MicroSD 149 */ 150 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 151 switch (index) { 152 case 0: 153 imx_iomux_v3_setup_multiple_pads( 154 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 155 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 156 usdhc_cfg[0].max_bus_width = 4; 157 gpio_direction_input(USDHC3_CD_GPIO); 158 break; 159 case 1: 160 imx_iomux_v3_setup_multiple_pads( 161 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 162 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 163 usdhc_cfg[1].max_bus_width = 4; 164 gpio_direction_input(USDHC1_CD_GPIO); 165 break; 166 default: 167 printf("Warning: you configured more USDHC controllers" 168 "(%d) then supported by the board (%d)\n", 169 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 170 return status; 171 } 172 173 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 174 } 175 176 return status; 177 } 178 179 static int mx6_rgmii_rework(struct phy_device *phydev) 180 { 181 unsigned short val; 182 183 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 184 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 185 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 186 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 187 188 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 189 val &= 0xffe3; 190 val |= 0x18; 191 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 192 193 /* introduce tx clock delay */ 194 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 195 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 196 val |= 0x0100; 197 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 198 199 return 0; 200 } 201 202 int board_phy_config(struct phy_device *phydev) 203 { 204 mx6_rgmii_rework(phydev); 205 206 if (phydev->drv->config) 207 phydev->drv->config(phydev); 208 209 return 0; 210 } 211 212 #if defined(CONFIG_VIDEO_IPUV3) 213 static struct fb_videomode const hdmi = { 214 .name = "HDMI", 215 .refresh = 60, 216 .xres = 1024, 217 .yres = 768, 218 .pixclock = 15385, 219 .left_margin = 220, 220 .right_margin = 40, 221 .upper_margin = 21, 222 .lower_margin = 7, 223 .hsync_len = 60, 224 .vsync_len = 10, 225 .sync = FB_SYNC_EXT, 226 .vmode = FB_VMODE_NONINTERLACED 227 }; 228 229 int board_video_skip(void) 230 { 231 int ret; 232 233 ret = ipuv3_fb_init(&hdmi, 0, IPU_PIX_FMT_RGB24); 234 235 if (ret) { 236 printf("HDMI cannot be configured: %d\n", ret); 237 return ret; 238 } 239 240 imx_enable_hdmi_phy(); 241 242 return ret; 243 } 244 245 static void setup_display(void) 246 { 247 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 248 int reg; 249 250 enable_ipu_clock(); 251 imx_setup_hdmi(); 252 253 reg = readl(&mxc_ccm->chsccdr); 254 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 255 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 256 writel(reg, &mxc_ccm->chsccdr); 257 } 258 #endif /* CONFIG_VIDEO_IPUV3 */ 259 260 int board_eth_init(bd_t *bis) 261 { 262 setup_iomux_enet(); 263 264 return cpu_eth_init(bis); 265 } 266 267 int board_early_init_f(void) 268 { 269 setup_iomux_uart(); 270 #if defined(CONFIG_VIDEO_IPUV3) 271 setup_display(); 272 #endif 273 return 0; 274 } 275 276 /* 277 * Do not overwrite the console 278 * Use always serial for U-Boot console 279 */ 280 int overwrite_console(void) 281 { 282 return 1; 283 } 284 285 #ifdef CONFIG_CMD_BMODE 286 static const struct boot_mode board_boot_modes[] = { 287 /* 4 bit bus width */ 288 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 289 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 290 {NULL, 0}, 291 }; 292 #endif 293 294 int board_late_init(void) 295 { 296 #ifdef CONFIG_CMD_BMODE 297 add_board_boot_modes(board_boot_modes); 298 #endif 299 300 return 0; 301 } 302 303 int board_init(void) 304 { 305 /* address of boot parameters */ 306 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 307 308 return 0; 309 } 310 311 int checkboard(void) 312 { 313 puts("Board: Wandboard\n"); 314 315 return 0; 316 } 317