1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014 O.S. Systems Software LTDA. 4 * 5 * Author: Fabio Estevam <fabio.estevam@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <asm/arch/clock.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mxc_hdmi.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <asm/imx-common/boot_mode.h> 21 #include <asm/imx-common/video.h> 22 #include <asm/io.h> 23 #include <linux/sizes.h> 24 #include <common.h> 25 #include <fsl_esdhc.h> 26 #include <mmc.h> 27 #include <miiphy.h> 28 #include <netdev.h> 29 #include <phy.h> 30 #include <input.h> 31 #include <i2c.h> 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 45 46 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 48 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 49 50 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) 51 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) 52 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) 53 54 int dram_init(void) 55 { 56 gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; 57 58 return 0; 59 } 60 61 static iomux_v3_cfg_t const uart1_pads[] = { 62 MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 63 MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), 64 }; 65 66 static iomux_v3_cfg_t const usdhc1_pads[] = { 67 MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72 MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 /* Carrier MicroSD Card Detect */ 74 MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), 75 }; 76 77 static iomux_v3_cfg_t const usdhc3_pads[] = { 78 MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 81 MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 82 MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 83 MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 84 /* SOM MicroSD Card Detect */ 85 MX6_PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), 86 }; 87 88 static iomux_v3_cfg_t const enet_pads[] = { 89 MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), 90 MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), 91 MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 92 MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 93 MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 94 MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 95 MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 96 MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 97 MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), 98 MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), 99 MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 100 MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 101 MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), 102 MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), 103 MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 104 /* AR8031 PHY Reset */ 105 MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), 106 }; 107 108 static void setup_iomux_uart(void) 109 { 110 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 111 } 112 113 static void setup_iomux_enet(void) 114 { 115 imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); 116 117 /* Reset AR8031 PHY */ 118 gpio_direction_output(ETH_PHY_RESET, 0); 119 udelay(500); 120 gpio_set_value(ETH_PHY_RESET, 1); 121 } 122 123 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 124 {USDHC3_BASE_ADDR}, 125 {USDHC1_BASE_ADDR}, 126 }; 127 128 int board_mmc_getcd(struct mmc *mmc) 129 { 130 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 131 int ret = 0; 132 133 switch (cfg->esdhc_base) { 134 case USDHC1_BASE_ADDR: 135 ret = !gpio_get_value(USDHC1_CD_GPIO); 136 break; 137 case USDHC3_BASE_ADDR: 138 ret = !gpio_get_value(USDHC3_CD_GPIO); 139 break; 140 } 141 142 return ret; 143 } 144 145 int board_mmc_init(bd_t *bis) 146 { 147 s32 status = 0; 148 u32 index = 0; 149 150 /* 151 * Following map is done: 152 * (U-boot device node) (Physical Port) 153 * mmc0 SOM MicroSD 154 * mmc1 Carrier board MicroSD 155 */ 156 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 157 switch (index) { 158 case 0: 159 imx_iomux_v3_setup_multiple_pads( 160 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 161 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 162 usdhc_cfg[0].max_bus_width = 4; 163 gpio_direction_input(USDHC3_CD_GPIO); 164 break; 165 case 1: 166 imx_iomux_v3_setup_multiple_pads( 167 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 168 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 169 usdhc_cfg[1].max_bus_width = 4; 170 gpio_direction_input(USDHC1_CD_GPIO); 171 break; 172 default: 173 printf("Warning: you configured more USDHC controllers" 174 "(%d) then supported by the board (%d)\n", 175 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 176 return status; 177 } 178 179 status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 180 } 181 182 return status; 183 } 184 185 static int mx6_rgmii_rework(struct phy_device *phydev) 186 { 187 unsigned short val; 188 189 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 190 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 191 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 192 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 193 194 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 195 val &= 0xffe3; 196 val |= 0x18; 197 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 198 199 /* introduce tx clock delay */ 200 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 201 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 202 val |= 0x0100; 203 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 204 205 return 0; 206 } 207 208 int board_phy_config(struct phy_device *phydev) 209 { 210 mx6_rgmii_rework(phydev); 211 212 if (phydev->drv->config) 213 phydev->drv->config(phydev); 214 215 return 0; 216 } 217 218 #if defined(CONFIG_VIDEO_IPUV3) 219 struct i2c_pads_info i2c2_pad_info = { 220 .scl = { 221 .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL 222 | MUX_PAD_CTRL(I2C_PAD_CTRL), 223 .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 224 | MUX_PAD_CTRL(I2C_PAD_CTRL), 225 .gp = IMX_GPIO_NR(4, 12) 226 }, 227 .sda = { 228 .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA 229 | MUX_PAD_CTRL(I2C_PAD_CTRL), 230 .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 231 | MUX_PAD_CTRL(I2C_PAD_CTRL), 232 .gp = IMX_GPIO_NR(4, 13) 233 } 234 }; 235 236 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { 237 MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, 238 MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */ 239 MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */ 240 MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04 241 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */ 242 MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */ 243 244 MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, 245 MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, 246 MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, 247 MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, 248 MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, 249 MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, 250 MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, 251 MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, 252 MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, 253 MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, 254 MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, 255 MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, 256 MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, 257 MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, 258 MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, 259 MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, 260 MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, 261 MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, 262 263 MX6_PAD_SD4_DAT2__GPIO2_IO10 264 | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */ 265 MX6_PAD_SD4_DAT3__GPIO2_IO11 266 | MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */ 267 }; 268 269 static void do_enable_hdmi(struct display_info_t const *dev) 270 { 271 imx_enable_hdmi_phy(); 272 } 273 274 static int detect_i2c(struct display_info_t const *dev) 275 { 276 return (0 == i2c_set_bus_num(dev->bus)) && 277 (0 == i2c_probe(dev->addr)); 278 } 279 280 static void enable_fwadapt_7wvga(struct display_info_t const *dev) 281 { 282 imx_iomux_v3_setup_multiple_pads( 283 fwadapt_7wvga_pads, 284 ARRAY_SIZE(fwadapt_7wvga_pads)); 285 286 gpio_direction_output(IMX_GPIO_NR(2, 10), 1); 287 gpio_direction_output(IMX_GPIO_NR(2, 11), 1); 288 } 289 290 struct display_info_t const displays[] = {{ 291 .bus = -1, 292 .addr = 0, 293 .pixfmt = IPU_PIX_FMT_RGB24, 294 .detect = detect_hdmi, 295 .enable = do_enable_hdmi, 296 .mode = { 297 .name = "HDMI", 298 .refresh = 60, 299 .xres = 1024, 300 .yres = 768, 301 .pixclock = 15385, 302 .left_margin = 220, 303 .right_margin = 40, 304 .upper_margin = 21, 305 .lower_margin = 7, 306 .hsync_len = 60, 307 .vsync_len = 10, 308 .sync = FB_SYNC_EXT, 309 .vmode = FB_VMODE_NONINTERLACED 310 } }, { 311 .bus = 1, 312 .addr = 0x10, 313 .pixfmt = IPU_PIX_FMT_RGB666, 314 .detect = detect_i2c, 315 .enable = enable_fwadapt_7wvga, 316 .mode = { 317 .name = "FWBADAPT-LCD-F07A-0102", 318 .refresh = 60, 319 .xres = 800, 320 .yres = 480, 321 .pixclock = 33260, 322 .left_margin = 128, 323 .right_margin = 128, 324 .upper_margin = 22, 325 .lower_margin = 22, 326 .hsync_len = 1, 327 .vsync_len = 1, 328 .sync = 0, 329 .vmode = FB_VMODE_NONINTERLACED 330 } } }; 331 size_t display_count = ARRAY_SIZE(displays); 332 333 static void setup_display(void) 334 { 335 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 336 int reg; 337 338 enable_ipu_clock(); 339 imx_setup_hdmi(); 340 341 reg = readl(&mxc_ccm->chsccdr); 342 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 343 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 344 writel(reg, &mxc_ccm->chsccdr); 345 346 /* Disable LCD backlight */ 347 imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20); 348 gpio_direction_input(IMX_GPIO_NR(4, 20)); 349 } 350 #endif /* CONFIG_VIDEO_IPUV3 */ 351 352 int board_eth_init(bd_t *bis) 353 { 354 setup_iomux_enet(); 355 356 return cpu_eth_init(bis); 357 } 358 359 int board_early_init_f(void) 360 { 361 setup_iomux_uart(); 362 #if defined(CONFIG_VIDEO_IPUV3) 363 setup_display(); 364 #endif 365 return 0; 366 } 367 368 /* 369 * Do not overwrite the console 370 * Use always serial for U-Boot console 371 */ 372 int overwrite_console(void) 373 { 374 return 1; 375 } 376 377 #ifdef CONFIG_CMD_BMODE 378 static const struct boot_mode board_boot_modes[] = { 379 /* 4 bit bus width */ 380 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 381 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 382 {NULL, 0}, 383 }; 384 #endif 385 386 int board_late_init(void) 387 { 388 #ifdef CONFIG_CMD_BMODE 389 add_board_boot_modes(board_boot_modes); 390 #endif 391 392 return 0; 393 } 394 395 int board_init(void) 396 { 397 /* address of boot parameters */ 398 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 399 400 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info); 401 402 return 0; 403 } 404 405 int checkboard(void) 406 { 407 puts("Board: Wandboard\n"); 408 409 return 0; 410 } 411