1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014 O.S. Systems Software LTDA. 4 * 5 * Author: Fabio Estevam <fabio.estevam@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <asm/arch/clock.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mxc_hdmi.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/imx-common/iomux-v3.h> 19 #include <asm/imx-common/mxc_i2c.h> 20 #include <asm/imx-common/boot_mode.h> 21 #include <asm/imx-common/video.h> 22 #include <asm/imx-common/sata.h> 23 #include <asm/io.h> 24 #include <linux/sizes.h> 25 #include <common.h> 26 #include <fsl_esdhc.h> 27 #include <mmc.h> 28 #include <miiphy.h> 29 #include <netdev.h> 30 #include <phy.h> 31 #include <input.h> 32 #include <i2c.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 37 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 38 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 41 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 42 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 44 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 45 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 46 47 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 48 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 49 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 50 51 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) 52 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) 53 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) 54 #define REV_DETECTION IMX_GPIO_NR(2, 28) 55 56 int dram_init(void) 57 { 58 gd->ram_size = imx_ddr_size(); 59 60 return 0; 61 } 62 63 static iomux_v3_cfg_t const uart1_pads[] = { 64 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 65 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 66 }; 67 68 static iomux_v3_cfg_t const usdhc1_pads[] = { 69 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 70 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 71 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 72 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 73 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 74 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 75 /* Carrier MicroSD Card Detect */ 76 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 77 }; 78 79 static iomux_v3_cfg_t const usdhc3_pads[] = { 80 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 81 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 82 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 83 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 84 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 85 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 86 /* SOM MicroSD Card Detect */ 87 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), 88 }; 89 90 static iomux_v3_cfg_t const enet_pads[] = { 91 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 92 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 93 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 94 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 95 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 96 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 97 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 98 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 99 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), 100 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 101 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 102 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 103 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 104 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 105 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 106 /* AR8031 PHY Reset */ 107 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 108 }; 109 110 static iomux_v3_cfg_t const rev_detection_pad[] = { 111 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 112 }; 113 114 static void setup_iomux_uart(void) 115 { 116 SETUP_IOMUX_PADS(uart1_pads); 117 } 118 119 static void setup_iomux_enet(void) 120 { 121 SETUP_IOMUX_PADS(enet_pads); 122 123 /* Reset AR8031 PHY */ 124 gpio_direction_output(ETH_PHY_RESET, 0); 125 mdelay(10); 126 gpio_set_value(ETH_PHY_RESET, 1); 127 udelay(100); 128 } 129 130 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 131 {USDHC3_BASE_ADDR}, 132 {USDHC1_BASE_ADDR}, 133 }; 134 135 int board_mmc_getcd(struct mmc *mmc) 136 { 137 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 138 int ret = 0; 139 140 switch (cfg->esdhc_base) { 141 case USDHC1_BASE_ADDR: 142 ret = !gpio_get_value(USDHC1_CD_GPIO); 143 break; 144 case USDHC3_BASE_ADDR: 145 ret = !gpio_get_value(USDHC3_CD_GPIO); 146 break; 147 } 148 149 return ret; 150 } 151 152 int board_mmc_init(bd_t *bis) 153 { 154 int ret; 155 u32 index = 0; 156 157 /* 158 * Following map is done: 159 * (U-Boot device node) (Physical Port) 160 * mmc0 SOM MicroSD 161 * mmc1 Carrier board MicroSD 162 */ 163 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 164 switch (index) { 165 case 0: 166 SETUP_IOMUX_PADS(usdhc3_pads); 167 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 168 usdhc_cfg[0].max_bus_width = 4; 169 gpio_direction_input(USDHC3_CD_GPIO); 170 break; 171 case 1: 172 SETUP_IOMUX_PADS(usdhc1_pads); 173 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 174 usdhc_cfg[1].max_bus_width = 4; 175 gpio_direction_input(USDHC1_CD_GPIO); 176 break; 177 default: 178 printf("Warning: you configured more USDHC controllers" 179 "(%d) then supported by the board (%d)\n", 180 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 181 return -EINVAL; 182 } 183 184 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 185 if (ret) 186 return ret; 187 } 188 189 return 0; 190 } 191 192 #if defined(CONFIG_VIDEO_IPUV3) 193 struct i2c_pads_info mx6q_i2c2_pad_info = { 194 .scl = { 195 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL 196 | MUX_PAD_CTRL(I2C_PAD_CTRL), 197 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 198 | MUX_PAD_CTRL(I2C_PAD_CTRL), 199 .gp = IMX_GPIO_NR(4, 12) 200 }, 201 .sda = { 202 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA 203 | MUX_PAD_CTRL(I2C_PAD_CTRL), 204 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 205 | MUX_PAD_CTRL(I2C_PAD_CTRL), 206 .gp = IMX_GPIO_NR(4, 13) 207 } 208 }; 209 210 struct i2c_pads_info mx6dl_i2c2_pad_info = { 211 .scl = { 212 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL 213 | MUX_PAD_CTRL(I2C_PAD_CTRL), 214 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 215 | MUX_PAD_CTRL(I2C_PAD_CTRL), 216 .gp = IMX_GPIO_NR(4, 12) 217 }, 218 .sda = { 219 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA 220 | MUX_PAD_CTRL(I2C_PAD_CTRL), 221 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 222 | MUX_PAD_CTRL(I2C_PAD_CTRL), 223 .gp = IMX_GPIO_NR(4, 13) 224 } 225 }; 226 227 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { 228 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), 229 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */ 230 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */ 231 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */ 232 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */ 233 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), 234 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), 235 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), 236 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), 237 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), 238 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), 239 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), 240 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), 241 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), 242 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), 243 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), 244 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), 245 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), 246 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), 247 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), 248 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), 249 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), 250 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), 251 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */ 252 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */ 253 }; 254 255 static void do_enable_hdmi(struct display_info_t const *dev) 256 { 257 imx_enable_hdmi_phy(); 258 } 259 260 static int detect_i2c(struct display_info_t const *dev) 261 { 262 return (0 == i2c_set_bus_num(dev->bus)) && 263 (0 == i2c_probe(dev->addr)); 264 } 265 266 static void enable_fwadapt_7wvga(struct display_info_t const *dev) 267 { 268 SETUP_IOMUX_PADS(fwadapt_7wvga_pads); 269 270 gpio_direction_output(IMX_GPIO_NR(2, 10), 1); 271 gpio_direction_output(IMX_GPIO_NR(2, 11), 1); 272 } 273 274 struct display_info_t const displays[] = {{ 275 .bus = -1, 276 .addr = 0, 277 .pixfmt = IPU_PIX_FMT_RGB24, 278 .detect = detect_hdmi, 279 .enable = do_enable_hdmi, 280 .mode = { 281 .name = "HDMI", 282 .refresh = 60, 283 .xres = 1024, 284 .yres = 768, 285 .pixclock = 15385, 286 .left_margin = 220, 287 .right_margin = 40, 288 .upper_margin = 21, 289 .lower_margin = 7, 290 .hsync_len = 60, 291 .vsync_len = 10, 292 .sync = FB_SYNC_EXT, 293 .vmode = FB_VMODE_NONINTERLACED 294 } }, { 295 .bus = 1, 296 .addr = 0x10, 297 .pixfmt = IPU_PIX_FMT_RGB666, 298 .detect = detect_i2c, 299 .enable = enable_fwadapt_7wvga, 300 .mode = { 301 .name = "FWBADAPT-LCD-F07A-0102", 302 .refresh = 60, 303 .xres = 800, 304 .yres = 480, 305 .pixclock = 33260, 306 .left_margin = 128, 307 .right_margin = 128, 308 .upper_margin = 22, 309 .lower_margin = 22, 310 .hsync_len = 1, 311 .vsync_len = 1, 312 .sync = 0, 313 .vmode = FB_VMODE_NONINTERLACED 314 } } }; 315 size_t display_count = ARRAY_SIZE(displays); 316 317 static void setup_display(void) 318 { 319 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 320 int reg; 321 322 enable_ipu_clock(); 323 imx_setup_hdmi(); 324 325 reg = readl(&mxc_ccm->chsccdr); 326 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 327 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 328 writel(reg, &mxc_ccm->chsccdr); 329 330 /* Disable LCD backlight */ 331 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20); 332 gpio_direction_input(IMX_GPIO_NR(4, 20)); 333 } 334 #endif /* CONFIG_VIDEO_IPUV3 */ 335 336 int board_eth_init(bd_t *bis) 337 { 338 setup_iomux_enet(); 339 340 return cpu_eth_init(bis); 341 } 342 343 int board_early_init_f(void) 344 { 345 setup_iomux_uart(); 346 #if defined(CONFIG_VIDEO_IPUV3) 347 setup_display(); 348 #endif 349 #ifdef CONFIG_CMD_SATA 350 /* Only mx6q wandboard has SATA */ 351 if (is_cpu_type(MXC_CPU_MX6Q)) 352 setup_sata(); 353 #endif 354 355 return 0; 356 } 357 358 /* 359 * Do not overwrite the console 360 * Use always serial for U-Boot console 361 */ 362 int overwrite_console(void) 363 { 364 return 1; 365 } 366 367 #ifdef CONFIG_CMD_BMODE 368 static const struct boot_mode board_boot_modes[] = { 369 /* 4 bit bus width */ 370 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 371 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 372 {NULL, 0}, 373 }; 374 #endif 375 376 static bool is_revc1(void) 377 { 378 SETUP_IOMUX_PADS(rev_detection_pad); 379 gpio_direction_input(REV_DETECTION); 380 381 if (gpio_get_value(REV_DETECTION)) 382 return true; 383 else 384 return false; 385 } 386 387 int board_late_init(void) 388 { 389 #ifdef CONFIG_CMD_BMODE 390 add_board_boot_modes(board_boot_modes); 391 #endif 392 393 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 394 if (is_mx6dq()) 395 setenv("board_rev", "MX6Q"); 396 else 397 setenv("board_rev", "MX6DL"); 398 399 if (is_revc1()) 400 setenv("board_name", "C1"); 401 else 402 setenv("board_name", "B1"); 403 #endif 404 return 0; 405 } 406 407 int board_init(void) 408 { 409 /* address of boot parameters */ 410 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 411 412 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); 413 if (is_mx6dq()) 414 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); 415 else 416 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); 417 418 return 0; 419 } 420 421 int checkboard(void) 422 { 423 if (is_revc1()) 424 puts("Board: Wandboard rev C1\n"); 425 else 426 puts("Board: Wandboard rev B1\n"); 427 428 return 0; 429 } 430