1 /* 2 * Copyright (C) 2013 Freescale Semiconductor, Inc. 3 * Copyright (C) 2014 O.S. Systems Software LTDA. 4 * 5 * Author: Fabio Estevam <fabio.estevam@freescale.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <asm/arch/clock.h> 11 #include <asm/arch/crm_regs.h> 12 #include <asm/arch/iomux.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mxc_hdmi.h> 16 #include <asm/arch/sys_proto.h> 17 #include <asm/gpio.h> 18 #include <asm/mach-imx/iomux-v3.h> 19 #include <asm/mach-imx/mxc_i2c.h> 20 #include <asm/mach-imx/boot_mode.h> 21 #include <asm/mach-imx/video.h> 22 #include <asm/mach-imx/sata.h> 23 #include <asm/io.h> 24 #include <linux/sizes.h> 25 #include <common.h> 26 #include <fsl_esdhc.h> 27 #include <mmc.h> 28 #include <miiphy.h> 29 #include <netdev.h> 30 #include <phy.h> 31 #include <input.h> 32 #include <i2c.h> 33 #include <power/pmic.h> 34 #include <power/pfuze100_pmic.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 39 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 40 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 42 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 43 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ 44 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 45 46 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 47 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 48 49 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 50 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ 51 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 52 53 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 2) 54 #define USDHC3_CD_GPIO IMX_GPIO_NR(3, 9) 55 #define ETH_PHY_RESET IMX_GPIO_NR(3, 29) 56 #define ETH_PHY_AR8035_POWER IMX_GPIO_NR(7, 13) 57 #define REV_DETECTION IMX_GPIO_NR(2, 28) 58 59 static bool with_pmic; 60 61 int dram_init(void) 62 { 63 gd->ram_size = imx_ddr_size(); 64 65 return 0; 66 } 67 68 static iomux_v3_cfg_t const uart1_pads[] = { 69 IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 70 IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)), 71 }; 72 73 static iomux_v3_cfg_t const usdhc1_pads[] = { 74 IOMUX_PADS(PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 75 IOMUX_PADS(PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 76 IOMUX_PADS(PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 77 IOMUX_PADS(PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 78 IOMUX_PADS(PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 79 IOMUX_PADS(PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 80 /* Carrier MicroSD Card Detect */ 81 IOMUX_PADS(PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL)), 82 }; 83 84 static iomux_v3_cfg_t const usdhc3_pads[] = { 85 IOMUX_PADS(PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 86 IOMUX_PADS(PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 87 IOMUX_PADS(PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 88 IOMUX_PADS(PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 89 IOMUX_PADS(PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 90 IOMUX_PADS(PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL)), 91 /* SOM MicroSD Card Detect */ 92 IOMUX_PADS(PAD_EIM_DA9__GPIO3_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL)), 93 }; 94 95 static iomux_v3_cfg_t const enet_pads[] = { 96 IOMUX_PADS(PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL)), 97 IOMUX_PADS(PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 98 IOMUX_PADS(PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 99 IOMUX_PADS(PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 100 IOMUX_PADS(PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 101 IOMUX_PADS(PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 102 IOMUX_PADS(PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 103 IOMUX_PADS(PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 104 IOMUX_PADS(PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL)), 105 IOMUX_PADS(PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL)), 106 IOMUX_PADS(PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 107 IOMUX_PADS(PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 108 IOMUX_PADS(PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 109 IOMUX_PADS(PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL)), 110 IOMUX_PADS(PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL)), 111 /* AR8031 PHY Reset */ 112 IOMUX_PADS(PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL)), 113 }; 114 115 static iomux_v3_cfg_t const enet_ar8035_power_pads[] = { 116 /* AR8035 POWER */ 117 IOMUX_PADS(PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)), 118 }; 119 120 static iomux_v3_cfg_t const rev_detection_pad[] = { 121 IOMUX_PADS(PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL)), 122 }; 123 124 static void setup_iomux_uart(void) 125 { 126 SETUP_IOMUX_PADS(uart1_pads); 127 } 128 129 static void setup_iomux_enet(void) 130 { 131 SETUP_IOMUX_PADS(enet_pads); 132 133 if (with_pmic) { 134 SETUP_IOMUX_PADS(enet_ar8035_power_pads); 135 /* enable AR8035 POWER */ 136 gpio_direction_output(ETH_PHY_AR8035_POWER, 0); 137 } 138 /* wait until 3.3V of PHY and clock become stable */ 139 mdelay(10); 140 141 /* Reset AR8031 PHY */ 142 gpio_direction_output(ETH_PHY_RESET, 0); 143 mdelay(10); 144 gpio_set_value(ETH_PHY_RESET, 1); 145 udelay(100); 146 } 147 148 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 149 {USDHC3_BASE_ADDR}, 150 {USDHC1_BASE_ADDR}, 151 }; 152 153 int board_mmc_getcd(struct mmc *mmc) 154 { 155 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 156 int ret = 0; 157 158 switch (cfg->esdhc_base) { 159 case USDHC1_BASE_ADDR: 160 ret = !gpio_get_value(USDHC1_CD_GPIO); 161 break; 162 case USDHC3_BASE_ADDR: 163 ret = !gpio_get_value(USDHC3_CD_GPIO); 164 break; 165 } 166 167 return ret; 168 } 169 170 int board_mmc_init(bd_t *bis) 171 { 172 int ret; 173 u32 index = 0; 174 175 /* 176 * Following map is done: 177 * (U-Boot device node) (Physical Port) 178 * mmc0 SOM MicroSD 179 * mmc1 Carrier board MicroSD 180 */ 181 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { 182 switch (index) { 183 case 0: 184 SETUP_IOMUX_PADS(usdhc3_pads); 185 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 186 usdhc_cfg[0].max_bus_width = 4; 187 gpio_direction_input(USDHC3_CD_GPIO); 188 break; 189 case 1: 190 SETUP_IOMUX_PADS(usdhc1_pads); 191 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 192 usdhc_cfg[1].max_bus_width = 4; 193 gpio_direction_input(USDHC1_CD_GPIO); 194 break; 195 default: 196 printf("Warning: you configured more USDHC controllers" 197 "(%d) then supported by the board (%d)\n", 198 index + 1, CONFIG_SYS_FSL_USDHC_NUM); 199 return -EINVAL; 200 } 201 202 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]); 203 if (ret) 204 return ret; 205 } 206 207 return 0; 208 } 209 210 static int ar8031_phy_fixup(struct phy_device *phydev) 211 { 212 unsigned short val; 213 int mask; 214 215 /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ 216 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); 217 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); 218 phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); 219 220 val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); 221 if (with_pmic) 222 mask = 0xffe7; /* AR8035 */ 223 else 224 mask = 0xffe3; /* AR8031 */ 225 226 val &= mask; 227 val |= 0x18; 228 phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); 229 230 /* introduce tx clock delay */ 231 phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); 232 val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); 233 val |= 0x0100; 234 phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); 235 236 return 0; 237 } 238 239 int board_phy_config(struct phy_device *phydev) 240 { 241 ar8031_phy_fixup(phydev); 242 243 if (phydev->drv->config) 244 phydev->drv->config(phydev); 245 246 return 0; 247 } 248 249 #if defined(CONFIG_VIDEO_IPUV3) 250 struct i2c_pads_info mx6q_i2c2_pad_info = { 251 .scl = { 252 .i2c_mode = MX6Q_PAD_KEY_COL3__I2C2_SCL 253 | MUX_PAD_CTRL(I2C_PAD_CTRL), 254 .gpio_mode = MX6Q_PAD_KEY_COL3__GPIO4_IO12 255 | MUX_PAD_CTRL(I2C_PAD_CTRL), 256 .gp = IMX_GPIO_NR(4, 12) 257 }, 258 .sda = { 259 .i2c_mode = MX6Q_PAD_KEY_ROW3__I2C2_SDA 260 | MUX_PAD_CTRL(I2C_PAD_CTRL), 261 .gpio_mode = MX6Q_PAD_KEY_ROW3__GPIO4_IO13 262 | MUX_PAD_CTRL(I2C_PAD_CTRL), 263 .gp = IMX_GPIO_NR(4, 13) 264 } 265 }; 266 267 struct i2c_pads_info mx6dl_i2c2_pad_info = { 268 .scl = { 269 .i2c_mode = MX6DL_PAD_KEY_COL3__I2C2_SCL 270 | MUX_PAD_CTRL(I2C_PAD_CTRL), 271 .gpio_mode = MX6DL_PAD_KEY_COL3__GPIO4_IO12 272 | MUX_PAD_CTRL(I2C_PAD_CTRL), 273 .gp = IMX_GPIO_NR(4, 12) 274 }, 275 .sda = { 276 .i2c_mode = MX6DL_PAD_KEY_ROW3__I2C2_SDA 277 | MUX_PAD_CTRL(I2C_PAD_CTRL), 278 .gpio_mode = MX6DL_PAD_KEY_ROW3__GPIO4_IO13 279 | MUX_PAD_CTRL(I2C_PAD_CTRL), 280 .gp = IMX_GPIO_NR(4, 13) 281 } 282 }; 283 284 struct i2c_pads_info mx6q_i2c3_pad_info = { 285 .scl = { 286 .i2c_mode = MX6Q_PAD_GPIO_5__I2C3_SCL 287 | MUX_PAD_CTRL(I2C_PAD_CTRL), 288 .gpio_mode = MX6Q_PAD_GPIO_5__GPIO1_IO05 289 | MUX_PAD_CTRL(I2C_PAD_CTRL), 290 .gp = IMX_GPIO_NR(1, 5) 291 }, 292 .sda = { 293 .i2c_mode = MX6Q_PAD_GPIO_16__I2C3_SDA 294 | MUX_PAD_CTRL(I2C_PAD_CTRL), 295 .gpio_mode = MX6Q_PAD_GPIO_16__GPIO7_IO11 296 | MUX_PAD_CTRL(I2C_PAD_CTRL), 297 .gp = IMX_GPIO_NR(7, 11) 298 } 299 }; 300 301 struct i2c_pads_info mx6dl_i2c3_pad_info = { 302 .scl = { 303 .i2c_mode = MX6DL_PAD_GPIO_5__I2C3_SCL 304 | MUX_PAD_CTRL(I2C_PAD_CTRL), 305 .gpio_mode = MX6DL_PAD_GPIO_5__GPIO1_IO05 306 | MUX_PAD_CTRL(I2C_PAD_CTRL), 307 .gp = IMX_GPIO_NR(1, 5) 308 }, 309 .sda = { 310 .i2c_mode = MX6DL_PAD_GPIO_16__I2C3_SDA 311 | MUX_PAD_CTRL(I2C_PAD_CTRL), 312 .gpio_mode = MX6DL_PAD_GPIO_16__GPIO7_IO11 313 | MUX_PAD_CTRL(I2C_PAD_CTRL), 314 .gp = IMX_GPIO_NR(7, 11) 315 } 316 }; 317 318 static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = { 319 IOMUX_PADS(PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK), 320 IOMUX_PADS(PAD_DI0_PIN2__IPU1_DI0_PIN02), /* HSync */ 321 IOMUX_PADS(PAD_DI0_PIN3__IPU1_DI0_PIN03), /* VSync */ 322 IOMUX_PADS(PAD_DI0_PIN4__IPU1_DI0_PIN04 | MUX_PAD_CTRL(PAD_CTL_DSE_120ohm)), /* Contrast */ 323 IOMUX_PADS(PAD_DI0_PIN15__IPU1_DI0_PIN15), /* DISP0_DRDY */ 324 IOMUX_PADS(PAD_DISP0_DAT0__IPU1_DISP0_DATA00), 325 IOMUX_PADS(PAD_DISP0_DAT1__IPU1_DISP0_DATA01), 326 IOMUX_PADS(PAD_DISP0_DAT2__IPU1_DISP0_DATA02), 327 IOMUX_PADS(PAD_DISP0_DAT3__IPU1_DISP0_DATA03), 328 IOMUX_PADS(PAD_DISP0_DAT4__IPU1_DISP0_DATA04), 329 IOMUX_PADS(PAD_DISP0_DAT5__IPU1_DISP0_DATA05), 330 IOMUX_PADS(PAD_DISP0_DAT6__IPU1_DISP0_DATA06), 331 IOMUX_PADS(PAD_DISP0_DAT7__IPU1_DISP0_DATA07), 332 IOMUX_PADS(PAD_DISP0_DAT8__IPU1_DISP0_DATA08), 333 IOMUX_PADS(PAD_DISP0_DAT9__IPU1_DISP0_DATA09), 334 IOMUX_PADS(PAD_DISP0_DAT10__IPU1_DISP0_DATA10), 335 IOMUX_PADS(PAD_DISP0_DAT11__IPU1_DISP0_DATA11), 336 IOMUX_PADS(PAD_DISP0_DAT12__IPU1_DISP0_DATA12), 337 IOMUX_PADS(PAD_DISP0_DAT13__IPU1_DISP0_DATA13), 338 IOMUX_PADS(PAD_DISP0_DAT14__IPU1_DISP0_DATA14), 339 IOMUX_PADS(PAD_DISP0_DAT15__IPU1_DISP0_DATA15), 340 IOMUX_PADS(PAD_DISP0_DAT16__IPU1_DISP0_DATA16), 341 IOMUX_PADS(PAD_DISP0_DAT17__IPU1_DISP0_DATA17), 342 IOMUX_PADS(PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_BKLEN */ 343 IOMUX_PADS(PAD_SD4_DAT3__GPIO2_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL)), /* DISP0_VDDEN */ 344 }; 345 346 static void do_enable_hdmi(struct display_info_t const *dev) 347 { 348 imx_enable_hdmi_phy(); 349 } 350 351 static int detect_i2c(struct display_info_t const *dev) 352 { 353 return (0 == i2c_set_bus_num(dev->bus)) && 354 (0 == i2c_probe(dev->addr)); 355 } 356 357 static void enable_fwadapt_7wvga(struct display_info_t const *dev) 358 { 359 SETUP_IOMUX_PADS(fwadapt_7wvga_pads); 360 361 gpio_direction_output(IMX_GPIO_NR(2, 10), 1); 362 gpio_direction_output(IMX_GPIO_NR(2, 11), 1); 363 } 364 365 struct display_info_t const displays[] = {{ 366 .bus = -1, 367 .addr = 0, 368 .pixfmt = IPU_PIX_FMT_RGB24, 369 .detect = detect_hdmi, 370 .enable = do_enable_hdmi, 371 .mode = { 372 .name = "HDMI", 373 .refresh = 60, 374 .xres = 1024, 375 .yres = 768, 376 .pixclock = 15385, 377 .left_margin = 220, 378 .right_margin = 40, 379 .upper_margin = 21, 380 .lower_margin = 7, 381 .hsync_len = 60, 382 .vsync_len = 10, 383 .sync = FB_SYNC_EXT, 384 .vmode = FB_VMODE_NONINTERLACED 385 } }, { 386 .bus = 1, 387 .addr = 0x10, 388 .pixfmt = IPU_PIX_FMT_RGB666, 389 .detect = detect_i2c, 390 .enable = enable_fwadapt_7wvga, 391 .mode = { 392 .name = "FWBADAPT-LCD-F07A-0102", 393 .refresh = 60, 394 .xres = 800, 395 .yres = 480, 396 .pixclock = 33260, 397 .left_margin = 128, 398 .right_margin = 128, 399 .upper_margin = 22, 400 .lower_margin = 22, 401 .hsync_len = 1, 402 .vsync_len = 1, 403 .sync = 0, 404 .vmode = FB_VMODE_NONINTERLACED 405 } } }; 406 size_t display_count = ARRAY_SIZE(displays); 407 408 static void setup_display(void) 409 { 410 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 411 int reg; 412 413 enable_ipu_clock(); 414 imx_setup_hdmi(); 415 416 reg = readl(&mxc_ccm->chsccdr); 417 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 418 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 419 writel(reg, &mxc_ccm->chsccdr); 420 421 /* Disable LCD backlight */ 422 SETUP_IOMUX_PAD(PAD_DI0_PIN4__GPIO4_IO20); 423 gpio_direction_input(IMX_GPIO_NR(4, 20)); 424 } 425 #endif /* CONFIG_VIDEO_IPUV3 */ 426 427 int board_eth_init(bd_t *bis) 428 { 429 setup_iomux_enet(); 430 431 return cpu_eth_init(bis); 432 } 433 434 int board_early_init_f(void) 435 { 436 setup_iomux_uart(); 437 #ifdef CONFIG_SATA 438 setup_sata(); 439 #endif 440 441 return 0; 442 } 443 444 #define PMIC_I2C_BUS 2 445 446 int power_init_board(void) 447 { 448 struct pmic *p; 449 u32 reg; 450 451 /* configure PFUZE100 PMIC */ 452 power_pfuze100_init(PMIC_I2C_BUS); 453 p = pmic_get("PFUZE100"); 454 if (p && !pmic_probe(p)) { 455 pmic_reg_read(p, PFUZE100_DEVICEID, ®); 456 printf("PMIC: PFUZE100 ID=0x%02x\n", reg); 457 with_pmic = true; 458 459 /* Set VGEN2 to 1.5V and enable */ 460 pmic_reg_read(p, PFUZE100_VGEN2VOL, ®); 461 reg &= ~(LDO_VOL_MASK); 462 reg |= (LDOA_1_50V | (1 << (LDO_EN))); 463 pmic_reg_write(p, PFUZE100_VGEN2VOL, reg); 464 } 465 466 return 0; 467 } 468 469 /* 470 * Do not overwrite the console 471 * Use always serial for U-Boot console 472 */ 473 int overwrite_console(void) 474 { 475 return 1; 476 } 477 478 #ifdef CONFIG_CMD_BMODE 479 static const struct boot_mode board_boot_modes[] = { 480 /* 4 bit bus width */ 481 {"mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)}, 482 {"mmc1", MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)}, 483 {NULL, 0}, 484 }; 485 #endif 486 487 static bool is_revc1(void) 488 { 489 SETUP_IOMUX_PADS(rev_detection_pad); 490 gpio_direction_input(REV_DETECTION); 491 492 if (gpio_get_value(REV_DETECTION)) 493 return true; 494 else 495 return false; 496 } 497 498 static bool is_revd1(void) 499 { 500 if (with_pmic) 501 return true; 502 else 503 return false; 504 } 505 506 int board_late_init(void) 507 { 508 #ifdef CONFIG_CMD_BMODE 509 add_board_boot_modes(board_boot_modes); 510 #endif 511 512 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 513 if (is_mx6dqp()) 514 env_set("board_rev", "MX6QP"); 515 else if (is_mx6dq()) 516 env_set("board_rev", "MX6Q"); 517 else 518 env_set("board_rev", "MX6DL"); 519 520 if (is_revd1()) 521 env_set("board_name", "D1"); 522 else if (is_revc1()) 523 env_set("board_name", "C1"); 524 else 525 env_set("board_name", "B1"); 526 #endif 527 return 0; 528 } 529 530 int board_init(void) 531 { 532 /* address of boot parameters */ 533 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 534 535 #if defined(CONFIG_VIDEO_IPUV3) 536 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); 537 if (is_mx6dq() || is_mx6dqp()) { 538 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info); 539 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info); 540 } else { 541 setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info); 542 setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info); 543 } 544 545 setup_display(); 546 #endif 547 548 return 0; 549 } 550 551 int checkboard(void) 552 { 553 if (is_revd1()) 554 puts("Board: Wandboard rev D1\n"); 555 else if (is_revc1()) 556 puts("Board: Wandboard rev C1\n"); 557 else 558 puts("Board: Wandboard rev B1\n"); 559 560 return 0; 561 } 562