1 /* 2 * mux.c 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <common.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/mux.h> 20 #include <asm/io.h> 21 #include <i2c.h> 22 #include "board.h" 23 24 static struct module_pin_mux uart0_pin_mux[] = { 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 27 {-1}, 28 }; 29 30 static struct module_pin_mux uart1_pin_mux[] = { 31 {OFFSET(uart1_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART1_RXD */ 32 {OFFSET(uart1_txd), (MODE(0) | PULLUDEN)}, /* UART1_TXD */ 33 {-1}, 34 }; 35 36 static struct module_pin_mux uart2_pin_mux[] = { 37 {OFFSET(spi0_sclk), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART2_RXD */ 38 {OFFSET(spi0_d0), (MODE(1) | PULLUDEN)}, /* UART2_TXD */ 39 {-1}, 40 }; 41 42 static struct module_pin_mux uart3_pin_mux[] = { 43 {OFFSET(spi0_cs1), (MODE(1) | PULLUP_EN | RXACTIVE)}, /* UART3_RXD */ 44 {OFFSET(ecap0_in_pwm0_out), (MODE(1) | PULLUDEN)}, /* UART3_TXD */ 45 {-1}, 46 }; 47 48 static struct module_pin_mux uart4_pin_mux[] = { 49 {OFFSET(gpmc_wait0), (MODE(6) | PULLUP_EN | RXACTIVE)}, /* UART4_RXD */ 50 {OFFSET(gpmc_wpn), (MODE(6) | PULLUDEN)}, /* UART4_TXD */ 51 {-1}, 52 }; 53 54 static struct module_pin_mux uart5_pin_mux[] = { 55 {OFFSET(lcd_data9), (MODE(4) | PULLUP_EN | RXACTIVE)}, /* UART5_RXD */ 56 {OFFSET(lcd_data8), (MODE(4) | PULLUDEN)}, /* UART5_TXD */ 57 {-1}, 58 }; 59 60 static struct module_pin_mux mmc0_pin_mux[] = { 61 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 62 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 63 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 64 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 65 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 66 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 67 //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 68 {-1}, 69 }; 70 71 static struct module_pin_mux i2c0_pin_mux[] = { 72 {OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | 73 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 74 {OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | 75 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 76 {-1}, 77 }; 78 79 static struct module_pin_mux i2c1_pin_mux[] = { 80 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | 81 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 82 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | 83 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 84 {-1}, 85 }; 86 87 static struct module_pin_mux gpio0_7_pin_mux[] = { 88 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ 89 {-1}, 90 }; 91 92 static struct module_pin_mux rmii1_pin_mux[] = { 93 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ 94 {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ 95 {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ 96 {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ 97 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ 98 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ 99 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ 100 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 101 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 102 {-1}, 103 }; 104 105 static struct module_pin_mux rgmii2_pin_mux[] = { 106 {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ 107 {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 108 {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ 109 {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ 110 {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ 111 {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ 112 {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ 113 {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 114 {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 115 {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 116 {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 117 {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 118 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 119 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 120 {-1}, 121 }; 122 123 static struct module_pin_mux nand_pin_mux[] = { 124 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 125 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 126 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 127 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 128 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 129 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 130 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 131 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 132 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 133 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 134 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 135 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 136 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 137 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 138 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 139 {-1}, 140 }; 141 142 void enable_uart0_pin_mux(void) 143 { 144 configure_module_pin_mux(uart0_pin_mux); 145 } 146 147 void enable_uart1_pin_mux(void) 148 { 149 configure_module_pin_mux(uart1_pin_mux); 150 } 151 152 void enable_uart2_pin_mux(void) 153 { 154 configure_module_pin_mux(uart2_pin_mux); 155 } 156 157 void enable_uart3_pin_mux(void) 158 { 159 configure_module_pin_mux(uart3_pin_mux); 160 } 161 162 void enable_uart4_pin_mux(void) 163 { 164 configure_module_pin_mux(uart4_pin_mux); 165 } 166 167 void enable_uart5_pin_mux(void) 168 { 169 configure_module_pin_mux(uart5_pin_mux); 170 } 171 172 void enable_i2c0_pin_mux(void) 173 { 174 configure_module_pin_mux(i2c0_pin_mux); 175 } 176 177 void enable_i2c1_pin_mux(void) 178 { 179 configure_module_pin_mux(i2c1_pin_mux); 180 } 181 182 void enable_board_pin_mux() 183 { 184 /* Baltos */ 185 configure_module_pin_mux(i2c1_pin_mux); 186 configure_module_pin_mux(gpio0_7_pin_mux); 187 configure_module_pin_mux(rgmii2_pin_mux); 188 configure_module_pin_mux(rmii1_pin_mux); 189 configure_module_pin_mux(mmc0_pin_mux); 190 191 #if defined(CONFIG_NAND) 192 configure_module_pin_mux(nand_pin_mux); 193 #endif 194 } 195