1 /* 2 * mux.c 3 * 4 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation version 2. 9 * 10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11 * kind, whether express or implied; without even the implied warranty 12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <common.h> 17 #include <asm/arch/sys_proto.h> 18 #include <asm/arch/hardware.h> 19 #include <asm/arch/mux.h> 20 #include <asm/io.h> 21 #include <i2c.h> 22 #include "board.h" 23 24 static struct module_pin_mux uart0_pin_mux[] = { 25 {OFFSET(uart0_rxd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */ 26 {OFFSET(uart0_txd), (MODE(0) | PULLUDEN)}, /* UART0_TXD */ 27 {-1}, 28 }; 29 30 static struct module_pin_mux mmc0_pin_mux[] = { 31 {OFFSET(mmc0_dat3), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT3 */ 32 {OFFSET(mmc0_dat2), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT2 */ 33 {OFFSET(mmc0_dat1), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT1 */ 34 {OFFSET(mmc0_dat0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_DAT0 */ 35 {OFFSET(mmc0_clk), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CLK */ 36 {OFFSET(mmc0_cmd), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* MMC0_CMD */ 37 //{OFFSET(spi0_cs1), (MODE(5) | RXACTIVE | PULLUP_EN)}, /* MMC0_CD */ 38 {-1}, 39 }; 40 41 static struct module_pin_mux i2c1_pin_mux[] = { 42 {OFFSET(spi0_d1), (MODE(2) | RXACTIVE | 43 PULLUDEN | SLEWCTRL)}, /* I2C_DATA */ 44 {OFFSET(spi0_cs0), (MODE(2) | RXACTIVE | 45 PULLUDEN | SLEWCTRL)}, /* I2C_SCLK */ 46 {-1}, 47 }; 48 49 static struct module_pin_mux gpio0_7_pin_mux[] = { 50 {OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN)}, /* GPIO0_7 */ 51 {-1}, 52 }; 53 54 static struct module_pin_mux rmii1_pin_mux[] = { 55 {OFFSET(mii1_crs), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ 56 {OFFSET(mii1_txen), MODE(1)}, /* RGMII1_TCTL */ 57 {OFFSET(mii1_txd1), MODE(1)}, /* RGMII1_TCTL */ 58 {OFFSET(mii1_txd0), MODE(1)}, /* RGMII1_TCTL */ 59 {OFFSET(mii1_rxd1), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ 60 {OFFSET(mii1_rxd0), MODE(1) | RXACTIVE}, /* RGMII1_TCTL */ 61 {OFFSET(rmii1_refclk), MODE(0) | RXACTIVE}, /* RGMII1_TCTL */ 62 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 63 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 64 {-1}, 65 }; 66 67 static struct module_pin_mux rgmii2_pin_mux[] = { 68 {OFFSET(gpmc_a0), MODE(2)}, /* RGMII1_TCTL */ 69 {OFFSET(gpmc_a1), MODE(2) | RXACTIVE}, /* RGMII1_RCTL */ 70 {OFFSET(gpmc_a2), MODE(2)}, /* RGMII1_TD3 */ 71 {OFFSET(gpmc_a3), MODE(2)}, /* RGMII1_TD2 */ 72 {OFFSET(gpmc_a4), MODE(2)}, /* RGMII1_TD1 */ 73 {OFFSET(gpmc_a5), MODE(2)}, /* RGMII1_TD0 */ 74 {OFFSET(gpmc_a6), MODE(2)}, /* RGMII1_TCLK */ 75 {OFFSET(gpmc_a7), MODE(2) | RXACTIVE}, /* RGMII1_RCLK */ 76 {OFFSET(gpmc_a8), MODE(2) | RXACTIVE}, /* RGMII1_RD3 */ 77 {OFFSET(gpmc_a9), MODE(2) | RXACTIVE}, /* RGMII1_RD2 */ 78 {OFFSET(gpmc_a10), MODE(2) | RXACTIVE}, /* RGMII1_RD1 */ 79 {OFFSET(gpmc_a11), MODE(2) | RXACTIVE}, /* RGMII1_RD0 */ 80 {OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */ 81 {OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */ 82 {-1}, 83 }; 84 85 static struct module_pin_mux nand_pin_mux[] = { 86 {OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */ 87 {OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */ 88 {OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */ 89 {OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */ 90 {OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */ 91 {OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */ 92 {OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */ 93 {OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */ 94 {OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */ 95 {OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */ 96 {OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */ 97 {OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */ 98 {OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */ 99 {OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */ 100 {OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */ 101 {-1}, 102 }; 103 104 void enable_uart0_pin_mux(void) 105 { 106 configure_module_pin_mux(uart0_pin_mux); 107 } 108 109 void enable_i2c1_pin_mux(void) 110 { 111 configure_module_pin_mux(i2c1_pin_mux); 112 } 113 114 void enable_board_pin_mux() 115 { 116 configure_module_pin_mux(i2c1_pin_mux); 117 configure_module_pin_mux(gpio0_7_pin_mux); 118 configure_module_pin_mux(rgmii2_pin_mux); 119 configure_module_pin_mux(rmii1_pin_mux); 120 configure_module_pin_mux(mmc0_pin_mux); 121 122 #if defined(CONFIG_NAND) 123 configure_module_pin_mux(nand_pin_mux); 124 #endif 125 } 126