xref: /openbmc/u-boot/board/vscom/baltos/board.c (revision 1494cc89)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * board.c
4  *
5  * Board functions for TI AM335X based boards
6  *
7  * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
8  */
9 
10 #include <common.h>
11 #include <errno.h>
12 #include <linux/libfdt.h>
13 #include <spl.h>
14 #include <asm/arch/cpu.h>
15 #include <asm/arch/hardware.h>
16 #include <asm/arch/omap.h>
17 #include <asm/arch/ddr_defs.h>
18 #include <asm/arch/clock.h>
19 #include <asm/arch/gpio.h>
20 #include <asm/arch/mmc_host_def.h>
21 #include <asm/arch/sys_proto.h>
22 #include <asm/arch/mem.h>
23 #include <asm/arch/mux.h>
24 #include <asm/io.h>
25 #include <asm/emif.h>
26 #include <asm/gpio.h>
27 #include <i2c.h>
28 #include <miiphy.h>
29 #include <cpsw.h>
30 #include <power/tps65217.h>
31 #include <power/tps65910.h>
32 #include <environment.h>
33 #include <watchdog.h>
34 #include "board.h"
35 
36 DECLARE_GLOBAL_DATA_PTR;
37 
38 /* GPIO that controls power to DDR on EVM-SK */
39 #define GPIO_DDR_VTT_EN		7
40 #define DIP_S1			44
41 #define MPCIE_SW		100
42 
43 static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
44 
45 static int baltos_set_console(void)
46 {
47 	int val, i, dips = 0;
48 	char buf[7];
49 
50 	for (i = 0; i < 4; i++) {
51 		sprintf(buf, "dip_s%d", i + 1);
52 
53 		if (gpio_request(DIP_S1 + i, buf)) {
54 			printf("failed to export GPIO %d\n", DIP_S1 + i);
55 			return 0;
56 		}
57 
58 		if (gpio_direction_input(DIP_S1 + i)) {
59 			printf("failed to set GPIO %d direction\n", DIP_S1 + i);
60 			return 0;
61 		}
62 
63 		val = gpio_get_value(DIP_S1 + i);
64 		dips |= val << i;
65 	}
66 
67 	printf("DIPs: 0x%1x\n", (~dips) & 0xf);
68 
69 	if ((dips & 0xf) == 0xe)
70 		env_set("console", "ttyUSB0,115200n8");
71 
72 	return 0;
73 }
74 
75 static int read_eeprom(BSP_VS_HWPARAM *header)
76 {
77 	i2c_set_bus_num(1);
78 
79 	/* Check if baseboard eeprom is available */
80 	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
81 		puts("Could not probe the EEPROM; something fundamentally "
82 			"wrong on the I2C bus.\n");
83 		return -ENODEV;
84 	}
85 
86 	/* read the eeprom using i2c */
87 	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
88 		     sizeof(BSP_VS_HWPARAM))) {
89 		puts("Could not read the EEPROM; something fundamentally"
90 			" wrong on the I2C bus.\n");
91 		return -EIO;
92 	}
93 
94 	if (header->Magic != 0xDEADBEEF) {
95 
96 		printf("Incorrect magic number (0x%x) in EEPROM\n",
97 				header->Magic);
98 
99 		/* fill default values */
100 		header->SystemId = 211;
101 		header->MAC1[0] = 0x00;
102 		header->MAC1[1] = 0x00;
103 		header->MAC1[2] = 0x00;
104 		header->MAC1[3] = 0x00;
105 		header->MAC1[4] = 0x00;
106 		header->MAC1[5] = 0x01;
107 
108 		header->MAC2[0] = 0x00;
109 		header->MAC2[1] = 0x00;
110 		header->MAC2[2] = 0x00;
111 		header->MAC2[3] = 0x00;
112 		header->MAC2[4] = 0x00;
113 		header->MAC2[5] = 0x02;
114 
115 		header->MAC3[0] = 0x00;
116 		header->MAC3[1] = 0x00;
117 		header->MAC3[2] = 0x00;
118 		header->MAC3[3] = 0x00;
119 		header->MAC3[4] = 0x00;
120 		header->MAC3[5] = 0x03;
121 	}
122 
123 	return 0;
124 }
125 
126 #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT)
127 
128 static const struct ddr_data ddr3_baltos_data = {
129 	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
130 	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
131 	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
132 	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
133 };
134 
135 static const struct cmd_control ddr3_baltos_cmd_ctrl_data = {
136 	.cmd0csratio = MT41K256M16HA125E_RATIO,
137 	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
138 
139 	.cmd1csratio = MT41K256M16HA125E_RATIO,
140 	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
141 
142 	.cmd2csratio = MT41K256M16HA125E_RATIO,
143 	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
144 };
145 
146 static struct emif_regs ddr3_baltos_emif_reg_data = {
147 	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
148 	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
149 	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
150 	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
151 	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
152 	.zq_config = MT41K256M16HA125E_ZQ_CFG,
153 	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
154 };
155 
156 #ifdef CONFIG_SPL_OS_BOOT
157 int spl_start_uboot(void)
158 {
159 	/* break into full u-boot on 'c' */
160 	return (serial_tstc() && serial_getc() == 'c');
161 }
162 #endif
163 
164 #define OSC	(V_OSCK/1000000)
165 const struct dpll_params dpll_ddr = {
166 		266, OSC-1, 1, -1, -1, -1, -1};
167 const struct dpll_params dpll_ddr_evm_sk = {
168 		303, OSC-1, 1, -1, -1, -1, -1};
169 const struct dpll_params dpll_ddr_baltos = {
170 		400, OSC-1, 1, -1, -1, -1, -1};
171 
172 void am33xx_spl_board_init(void)
173 {
174 	int mpu_vdd;
175 	int sil_rev;
176 
177 	/* Get the frequency */
178 	dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
179 
180 	/*
181 	 * The GP EVM, IDK and EVM SK use a TPS65910 PMIC.  For all
182 	 * MPU frequencies we support we use a CORE voltage of
183 	 * 1.1375V.  For MPU voltage we need to switch based on
184 	 * the frequency we are running at.
185 	 */
186 	i2c_set_bus_num(1);
187 
188 	printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED);
189 
190 	if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) {
191 		puts("i2c: cannot access TPS65910\n");
192 		return;
193 	}
194 
195 	/*
196 	 * Depending on MPU clock and PG we will need a different
197 	 * VDD to drive at that speed.
198 	 */
199 	sil_rev = readl(&cdev->deviceid) >> 28;
200 	mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev,
201 					      dpll_mpu_opp100.m);
202 
203 	/* Tell the TPS65910 to use i2c */
204 	tps65910_set_i2c_control();
205 
206 	/* First update MPU voltage. */
207 	if (tps65910_voltage_update(MPU, mpu_vdd))
208 		return;
209 
210 	/* Second, update the CORE voltage. */
211 	if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3))
212 		return;
213 
214 	/* Set CORE Frequencies to OPP100 */
215 	do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
216 
217 	/* Set MPU Frequency to what we detected now that voltages are set */
218 	do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
219 
220 	writel(0x000010ff, PRM_DEVICE_INST + 4);
221 }
222 
223 const struct dpll_params *get_dpll_ddr_params(void)
224 {
225 	enable_i2c1_pin_mux();
226 	i2c_set_bus_num(1);
227 
228 	return &dpll_ddr_baltos;
229 }
230 
231 void set_uart_mux_conf(void)
232 {
233 	enable_uart0_pin_mux();
234 }
235 
236 void set_mux_conf_regs(void)
237 {
238 	enable_board_pin_mux();
239 }
240 
241 const struct ctrl_ioregs ioregs_baltos = {
242 	.cm0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
243 	.cm1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
244 	.cm2ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
245 	.dt0ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
246 	.dt1ioctl		= MT41K256M16HA125E_IOCTRL_VALUE,
247 };
248 
249 void sdram_init(void)
250 {
251 	gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en");
252 	gpio_direction_output(GPIO_DDR_VTT_EN, 1);
253 
254 	config_ddr(400, &ioregs_baltos,
255 		   &ddr3_baltos_data,
256 		   &ddr3_baltos_cmd_ctrl_data,
257 		   &ddr3_baltos_emif_reg_data, 0);
258 }
259 #endif
260 
261 /*
262  * Basic board specific setup.  Pinmux has been handled already.
263  */
264 int board_init(void)
265 {
266 #if defined(CONFIG_HW_WATCHDOG)
267 	hw_watchdog_init();
268 #endif
269 
270 	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
271 #if defined(CONFIG_NOR) || defined(CONFIG_NAND)
272 	gpmc_init();
273 #endif
274 	return 0;
275 }
276 
277 int ft_board_setup(void *blob, bd_t *bd)
278 {
279 	int node, ret;
280 	unsigned char mac_addr[6];
281 	BSP_VS_HWPARAM header;
282 
283 	/* get production data */
284 	if (read_eeprom(&header))
285 		return 0;
286 
287 	/* setup MAC1 */
288 	mac_addr[0] = header.MAC1[0];
289 	mac_addr[1] = header.MAC1[1];
290 	mac_addr[2] = header.MAC1[2];
291 	mac_addr[3] = header.MAC1[3];
292 	mac_addr[4] = header.MAC1[4];
293 	mac_addr[5] = header.MAC1[5];
294 
295 
296 	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200");
297 	if (node < 0) {
298 		printf("no /soc/fman/ethernet path offset\n");
299 		return -ENODEV;
300 	}
301 
302 	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
303 	if (ret) {
304 		printf("error setting local-mac-address property\n");
305 		return -ENODEV;
306 	}
307 
308 	/* setup MAC2 */
309 	mac_addr[0] = header.MAC2[0];
310 	mac_addr[1] = header.MAC2[1];
311 	mac_addr[2] = header.MAC2[2];
312 	mac_addr[3] = header.MAC2[3];
313 	mac_addr[4] = header.MAC2[4];
314 	mac_addr[5] = header.MAC2[5];
315 
316 	node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300");
317 	if (node < 0) {
318 		printf("no /soc/fman/ethernet path offset\n");
319 		return -ENODEV;
320 	}
321 
322 	ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6);
323 	if (ret) {
324 		printf("error setting local-mac-address property\n");
325 		return -ENODEV;
326 	}
327 
328 	printf("\nFDT was successfully setup\n");
329 
330 	return 0;
331 }
332 
333 static struct module_pin_mux pcie_sw_pin_mux[] = {
334 	{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )},     /* GPIO3_4 */
335 	{-1},
336 };
337 
338 static struct module_pin_mux dip_pin_mux[] = {
339 	{OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )},	/* GPIO1_12 */
340 	{OFFSET(gpmc_ad13), (MODE(7)  | RXACTIVE )},	/* GPIO1_13 */
341 	{OFFSET(gpmc_ad14), (MODE(7)  | RXACTIVE )},	/* GPIO1_14 */
342 	{OFFSET(gpmc_ad15), (MODE(7)  | RXACTIVE )},	/* GPIO1_15 */
343 	{-1},
344 };
345 
346 #ifdef CONFIG_BOARD_LATE_INIT
347 int board_late_init(void)
348 {
349 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
350 	BSP_VS_HWPARAM header;
351 	char model[4];
352 
353 	/* get production data */
354 	if (read_eeprom(&header)) {
355 		strcpy(model, "211");
356 	} else {
357 		sprintf(model, "%d", header.SystemId);
358 		if (header.SystemId == 215) {
359 			configure_module_pin_mux(dip_pin_mux);
360 			baltos_set_console();
361 		}
362 	}
363 
364 	/* turn power for the mPCIe slot */
365 	configure_module_pin_mux(pcie_sw_pin_mux);
366 	if (gpio_request(MPCIE_SW, "mpcie_sw")) {
367 		printf("failed to export GPIO %d\n", MPCIE_SW);
368 		return -ENODEV;
369 	}
370 	if (gpio_direction_output(MPCIE_SW, 1)) {
371 		printf("failed to set GPIO %d direction\n", MPCIE_SW);
372 		return -ENODEV;
373 	}
374 
375 	env_set("board_name", model);
376 #endif
377 
378 	return 0;
379 }
380 #endif
381 
382 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
383 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
384 static void cpsw_control(int enabled)
385 {
386 	/* VTP can be added here */
387 
388 	return;
389 }
390 
391 static struct cpsw_slave_data cpsw_slaves[] = {
392 	{
393 		.slave_reg_ofs	= 0x208,
394 		.sliver_reg_ofs	= 0xd80,
395 		.phy_addr	= 0,
396 	},
397 	{
398 		.slave_reg_ofs	= 0x308,
399 		.sliver_reg_ofs	= 0xdc0,
400 		.phy_addr	= 7,
401 	},
402 };
403 
404 static struct cpsw_platform_data cpsw_data = {
405 	.mdio_base		= CPSW_MDIO_BASE,
406 	.cpsw_base		= CPSW_BASE,
407 	.mdio_div		= 0xff,
408 	.channels		= 8,
409 	.cpdma_reg_ofs		= 0x800,
410 	.slaves			= 2,
411 	.slave_data		= cpsw_slaves,
412 	.active_slave		= 1,
413 	.ale_reg_ofs		= 0xd00,
414 	.ale_entries		= 1024,
415 	.host_port_reg_ofs	= 0x108,
416 	.hw_stats_reg_ofs	= 0x900,
417 	.bd_ram_ofs		= 0x2000,
418 	.mac_control		= (1 << 5),
419 	.control		= cpsw_control,
420 	.host_port_num		= 0,
421 	.version		= CPSW_CTRL_VERSION_2,
422 };
423 #endif
424 
425 #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USB_ETHER)) \
426 		&& defined(CONFIG_SPL_BUILD)) || \
427 	((defined(CONFIG_DRIVER_TI_CPSW) || \
428 	  defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \
429 	 !defined(CONFIG_SPL_BUILD))
430 int board_eth_init(bd_t *bis)
431 {
432 	int rv, n = 0;
433 	uint8_t mac_addr[6];
434 	uint32_t mac_hi, mac_lo;
435 
436 	/*
437 	 * Note here that we're using CPSW1 since that has a 1Gbit PHY while
438 	 * CSPW0 has a 100Mbit PHY.
439 	 *
440 	 * On product, CPSW1 maps to port labeled WAN.
441 	 */
442 
443 	/* try reading mac address from efuse */
444 	mac_lo = readl(&cdev->macid1l);
445 	mac_hi = readl(&cdev->macid1h);
446 	mac_addr[0] = mac_hi & 0xFF;
447 	mac_addr[1] = (mac_hi & 0xFF00) >> 8;
448 	mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
449 	mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
450 	mac_addr[4] = mac_lo & 0xFF;
451 	mac_addr[5] = (mac_lo & 0xFF00) >> 8;
452 
453 #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
454 	(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
455 	if (!env_get("ethaddr")) {
456 		printf("<ethaddr> not set. Validating first E-fuse MAC\n");
457 
458 		if (is_valid_ethaddr(mac_addr))
459 			eth_env_set_enetaddr("ethaddr", mac_addr);
460 	}
461 
462 #ifdef CONFIG_DRIVER_TI_CPSW
463 	writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel);
464 	cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII;
465 	rv = cpsw_register(&cpsw_data);
466 	if (rv < 0)
467 		printf("Error %d registering CPSW switch\n", rv);
468 	else
469 		n += rv;
470 #endif
471 
472 	/*
473 	 *
474 	 * CPSW RGMII Internal Delay Mode is not supported in all PVT
475 	 * operating points.  So we must set the TX clock delay feature
476 	 * in the AR8051 PHY.  Since we only support a single ethernet
477 	 * device in U-Boot, we only do this for the first instance.
478 	 */
479 #define AR8051_PHY_DEBUG_ADDR_REG	0x1d
480 #define AR8051_PHY_DEBUG_DATA_REG	0x1e
481 #define AR8051_DEBUG_RGMII_CLK_DLY_REG	0x5
482 #define AR8051_RGMII_TX_CLK_DLY		0x100
483 	const char *devname;
484 	devname = miiphy_get_current_dev();
485 
486 	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG,
487 			AR8051_DEBUG_RGMII_CLK_DLY_REG);
488 	miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG,
489 			AR8051_RGMII_TX_CLK_DLY);
490 #endif
491 	return n;
492 }
493 #endif
494