16ce89324SYegor Yefremov /* 26ce89324SYegor Yefremov * board.c 36ce89324SYegor Yefremov * 46ce89324SYegor Yefremov * Board functions for TI AM335X based boards 56ce89324SYegor Yefremov * 66ce89324SYegor Yefremov * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/ 76ce89324SYegor Yefremov * 86ce89324SYegor Yefremov * SPDX-License-Identifier: GPL-2.0+ 96ce89324SYegor Yefremov */ 106ce89324SYegor Yefremov 116ce89324SYegor Yefremov #include <common.h> 126ce89324SYegor Yefremov #include <errno.h> 1373223f0eSSimon Glass #include <libfdt.h> 146ce89324SYegor Yefremov #include <spl.h> 156ce89324SYegor Yefremov #include <asm/arch/cpu.h> 166ce89324SYegor Yefremov #include <asm/arch/hardware.h> 176ce89324SYegor Yefremov #include <asm/arch/omap.h> 186ce89324SYegor Yefremov #include <asm/arch/ddr_defs.h> 196ce89324SYegor Yefremov #include <asm/arch/clock.h> 206ce89324SYegor Yefremov #include <asm/arch/gpio.h> 216ce89324SYegor Yefremov #include <asm/arch/mmc_host_def.h> 226ce89324SYegor Yefremov #include <asm/arch/sys_proto.h> 236ce89324SYegor Yefremov #include <asm/arch/mem.h> 246ce89324SYegor Yefremov #include <asm/arch/mux.h> 256ce89324SYegor Yefremov #include <asm/io.h> 266ce89324SYegor Yefremov #include <asm/emif.h> 276ce89324SYegor Yefremov #include <asm/gpio.h> 286ce89324SYegor Yefremov #include <i2c.h> 296ce89324SYegor Yefremov #include <miiphy.h> 306ce89324SYegor Yefremov #include <cpsw.h> 316ce89324SYegor Yefremov #include <power/tps65217.h> 326ce89324SYegor Yefremov #include <power/tps65910.h> 336ce89324SYegor Yefremov #include <environment.h> 346ce89324SYegor Yefremov #include <watchdog.h> 356ce89324SYegor Yefremov #include "board.h" 366ce89324SYegor Yefremov 376ce89324SYegor Yefremov DECLARE_GLOBAL_DATA_PTR; 386ce89324SYegor Yefremov 396ce89324SYegor Yefremov /* GPIO that controls power to DDR on EVM-SK */ 406ce89324SYegor Yefremov #define GPIO_DDR_VTT_EN 7 416ce89324SYegor Yefremov #define DIP_S1 44 42dcf7f6f1SYegor Yefremov #define MPCIE_SW 100 436ce89324SYegor Yefremov 446ce89324SYegor Yefremov static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE; 456ce89324SYegor Yefremov 466ce89324SYegor Yefremov static int baltos_set_console(void) 476ce89324SYegor Yefremov { 486ce89324SYegor Yefremov int val, i, dips = 0; 496ce89324SYegor Yefremov char buf[7]; 506ce89324SYegor Yefremov 516ce89324SYegor Yefremov for (i = 0; i < 4; i++) { 526ce89324SYegor Yefremov sprintf(buf, "dip_s%d", i + 1); 536ce89324SYegor Yefremov 546ce89324SYegor Yefremov if (gpio_request(DIP_S1 + i, buf)) { 556ce89324SYegor Yefremov printf("failed to export GPIO %d\n", DIP_S1 + i); 566ce89324SYegor Yefremov return 0; 576ce89324SYegor Yefremov } 586ce89324SYegor Yefremov 596ce89324SYegor Yefremov if (gpio_direction_input(DIP_S1 + i)) { 606ce89324SYegor Yefremov printf("failed to set GPIO %d direction\n", DIP_S1 + i); 616ce89324SYegor Yefremov return 0; 626ce89324SYegor Yefremov } 636ce89324SYegor Yefremov 646ce89324SYegor Yefremov val = gpio_get_value(DIP_S1 + i); 656ce89324SYegor Yefremov dips |= val << i; 666ce89324SYegor Yefremov } 676ce89324SYegor Yefremov 686ce89324SYegor Yefremov printf("DIPs: 0x%1x\n", (~dips) & 0xf); 696ce89324SYegor Yefremov 706ce89324SYegor Yefremov if ((dips & 0xf) == 0xe) 71*382bee57SSimon Glass env_set("console", "ttyUSB0,115200n8"); 726ce89324SYegor Yefremov 736ce89324SYegor Yefremov return 0; 746ce89324SYegor Yefremov } 756ce89324SYegor Yefremov 766ce89324SYegor Yefremov static int read_eeprom(BSP_VS_HWPARAM *header) 776ce89324SYegor Yefremov { 786ce89324SYegor Yefremov i2c_set_bus_num(1); 796ce89324SYegor Yefremov 806ce89324SYegor Yefremov /* Check if baseboard eeprom is available */ 816ce89324SYegor Yefremov if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { 826ce89324SYegor Yefremov puts("Could not probe the EEPROM; something fundamentally " 836ce89324SYegor Yefremov "wrong on the I2C bus.\n"); 846ce89324SYegor Yefremov return -ENODEV; 856ce89324SYegor Yefremov } 866ce89324SYegor Yefremov 876ce89324SYegor Yefremov /* read the eeprom using i2c */ 886ce89324SYegor Yefremov if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, 896ce89324SYegor Yefremov sizeof(BSP_VS_HWPARAM))) { 906ce89324SYegor Yefremov puts("Could not read the EEPROM; something fundamentally" 916ce89324SYegor Yefremov " wrong on the I2C bus.\n"); 926ce89324SYegor Yefremov return -EIO; 936ce89324SYegor Yefremov } 946ce89324SYegor Yefremov 956ce89324SYegor Yefremov if (header->Magic != 0xDEADBEEF) { 966ce89324SYegor Yefremov 976ce89324SYegor Yefremov printf("Incorrect magic number (0x%x) in EEPROM\n", 986ce89324SYegor Yefremov header->Magic); 996ce89324SYegor Yefremov 1006ce89324SYegor Yefremov /* fill default values */ 1016ce89324SYegor Yefremov header->SystemId = 211; 1026ce89324SYegor Yefremov header->MAC1[0] = 0x00; 1036ce89324SYegor Yefremov header->MAC1[1] = 0x00; 1046ce89324SYegor Yefremov header->MAC1[2] = 0x00; 1056ce89324SYegor Yefremov header->MAC1[3] = 0x00; 1066ce89324SYegor Yefremov header->MAC1[4] = 0x00; 1076ce89324SYegor Yefremov header->MAC1[5] = 0x01; 1086ce89324SYegor Yefremov 1096ce89324SYegor Yefremov header->MAC2[0] = 0x00; 1106ce89324SYegor Yefremov header->MAC2[1] = 0x00; 1116ce89324SYegor Yefremov header->MAC2[2] = 0x00; 1126ce89324SYegor Yefremov header->MAC2[3] = 0x00; 1136ce89324SYegor Yefremov header->MAC2[4] = 0x00; 1146ce89324SYegor Yefremov header->MAC2[5] = 0x02; 1156ce89324SYegor Yefremov 1166ce89324SYegor Yefremov header->MAC3[0] = 0x00; 1176ce89324SYegor Yefremov header->MAC3[1] = 0x00; 1186ce89324SYegor Yefremov header->MAC3[2] = 0x00; 1196ce89324SYegor Yefremov header->MAC3[3] = 0x00; 1206ce89324SYegor Yefremov header->MAC3[4] = 0x00; 1216ce89324SYegor Yefremov header->MAC3[5] = 0x03; 1226ce89324SYegor Yefremov } 1236ce89324SYegor Yefremov 1246ce89324SYegor Yefremov return 0; 1256ce89324SYegor Yefremov } 1266ce89324SYegor Yefremov 1276ce89324SYegor Yefremov #if defined(CONFIG_SPL_BUILD) || defined(CONFIG_NOR_BOOT) 1286ce89324SYegor Yefremov 1296ce89324SYegor Yefremov static const struct ddr_data ddr3_baltos_data = { 1306ce89324SYegor Yefremov .datardsratio0 = MT41K256M16HA125E_RD_DQS, 1316ce89324SYegor Yefremov .datawdsratio0 = MT41K256M16HA125E_WR_DQS, 1326ce89324SYegor Yefremov .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE, 1336ce89324SYegor Yefremov .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA, 1346ce89324SYegor Yefremov }; 1356ce89324SYegor Yefremov 1366ce89324SYegor Yefremov static const struct cmd_control ddr3_baltos_cmd_ctrl_data = { 1376ce89324SYegor Yefremov .cmd0csratio = MT41K256M16HA125E_RATIO, 1386ce89324SYegor Yefremov .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 1396ce89324SYegor Yefremov 1406ce89324SYegor Yefremov .cmd1csratio = MT41K256M16HA125E_RATIO, 1416ce89324SYegor Yefremov .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 1426ce89324SYegor Yefremov 1436ce89324SYegor Yefremov .cmd2csratio = MT41K256M16HA125E_RATIO, 1446ce89324SYegor Yefremov .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT, 1456ce89324SYegor Yefremov }; 1466ce89324SYegor Yefremov 1476ce89324SYegor Yefremov static struct emif_regs ddr3_baltos_emif_reg_data = { 1486ce89324SYegor Yefremov .sdram_config = MT41K256M16HA125E_EMIF_SDCFG, 1496ce89324SYegor Yefremov .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF, 1506ce89324SYegor Yefremov .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1, 1516ce89324SYegor Yefremov .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2, 1526ce89324SYegor Yefremov .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3, 1536ce89324SYegor Yefremov .zq_config = MT41K256M16HA125E_ZQ_CFG, 1546ce89324SYegor Yefremov .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY, 1556ce89324SYegor Yefremov }; 1566ce89324SYegor Yefremov 1576ce89324SYegor Yefremov #ifdef CONFIG_SPL_OS_BOOT 1586ce89324SYegor Yefremov int spl_start_uboot(void) 1596ce89324SYegor Yefremov { 1606ce89324SYegor Yefremov /* break into full u-boot on 'c' */ 1616ce89324SYegor Yefremov return (serial_tstc() && serial_getc() == 'c'); 1626ce89324SYegor Yefremov } 1636ce89324SYegor Yefremov #endif 1646ce89324SYegor Yefremov 1656ce89324SYegor Yefremov #define OSC (V_OSCK/1000000) 1666ce89324SYegor Yefremov const struct dpll_params dpll_ddr = { 1676ce89324SYegor Yefremov 266, OSC-1, 1, -1, -1, -1, -1}; 1686ce89324SYegor Yefremov const struct dpll_params dpll_ddr_evm_sk = { 1696ce89324SYegor Yefremov 303, OSC-1, 1, -1, -1, -1, -1}; 1706ce89324SYegor Yefremov const struct dpll_params dpll_ddr_baltos = { 1716ce89324SYegor Yefremov 400, OSC-1, 1, -1, -1, -1, -1}; 1726ce89324SYegor Yefremov 1736ce89324SYegor Yefremov void am33xx_spl_board_init(void) 1746ce89324SYegor Yefremov { 1756ce89324SYegor Yefremov int mpu_vdd; 1766ce89324SYegor Yefremov int sil_rev; 1776ce89324SYegor Yefremov 1786ce89324SYegor Yefremov /* Get the frequency */ 1796ce89324SYegor Yefremov dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); 1806ce89324SYegor Yefremov 1816ce89324SYegor Yefremov /* 1826ce89324SYegor Yefremov * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all 1836ce89324SYegor Yefremov * MPU frequencies we support we use a CORE voltage of 1846ce89324SYegor Yefremov * 1.1375V. For MPU voltage we need to switch based on 1856ce89324SYegor Yefremov * the frequency we are running at. 1866ce89324SYegor Yefremov */ 1876ce89324SYegor Yefremov i2c_set_bus_num(1); 1886ce89324SYegor Yefremov 189e6b1b58bSYegor Yefremov printf("I2C speed: %d Hz\n", CONFIG_SYS_OMAP24_I2C_SPEED); 190e6b1b58bSYegor Yefremov 1916ce89324SYegor Yefremov if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { 1926ce89324SYegor Yefremov puts("i2c: cannot access TPS65910\n"); 1936ce89324SYegor Yefremov return; 1946ce89324SYegor Yefremov } 1956ce89324SYegor Yefremov 1966ce89324SYegor Yefremov /* 1976ce89324SYegor Yefremov * Depending on MPU clock and PG we will need a different 1986ce89324SYegor Yefremov * VDD to drive at that speed. 1996ce89324SYegor Yefremov */ 2006ce89324SYegor Yefremov sil_rev = readl(&cdev->deviceid) >> 28; 2016ce89324SYegor Yefremov mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, 2026ce89324SYegor Yefremov dpll_mpu_opp100.m); 2036ce89324SYegor Yefremov 2046ce89324SYegor Yefremov /* Tell the TPS65910 to use i2c */ 2056ce89324SYegor Yefremov tps65910_set_i2c_control(); 2066ce89324SYegor Yefremov 2076ce89324SYegor Yefremov /* First update MPU voltage. */ 2086ce89324SYegor Yefremov if (tps65910_voltage_update(MPU, mpu_vdd)) 2096ce89324SYegor Yefremov return; 2106ce89324SYegor Yefremov 2116ce89324SYegor Yefremov /* Second, update the CORE voltage. */ 2126ce89324SYegor Yefremov if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) 2136ce89324SYegor Yefremov return; 2146ce89324SYegor Yefremov 2156ce89324SYegor Yefremov /* Set CORE Frequencies to OPP100 */ 2166ce89324SYegor Yefremov do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); 2176ce89324SYegor Yefremov 2186ce89324SYegor Yefremov /* Set MPU Frequency to what we detected now that voltages are set */ 2196ce89324SYegor Yefremov do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); 2206ce89324SYegor Yefremov 2216ce89324SYegor Yefremov writel(0x000010ff, PRM_DEVICE_INST + 4); 2226ce89324SYegor Yefremov } 2236ce89324SYegor Yefremov 2246ce89324SYegor Yefremov const struct dpll_params *get_dpll_ddr_params(void) 2256ce89324SYegor Yefremov { 2266ce89324SYegor Yefremov enable_i2c1_pin_mux(); 2276ce89324SYegor Yefremov i2c_set_bus_num(1); 2286ce89324SYegor Yefremov 2296ce89324SYegor Yefremov return &dpll_ddr_baltos; 2306ce89324SYegor Yefremov } 2316ce89324SYegor Yefremov 2326ce89324SYegor Yefremov void set_uart_mux_conf(void) 2336ce89324SYegor Yefremov { 2346ce89324SYegor Yefremov enable_uart0_pin_mux(); 2356ce89324SYegor Yefremov } 2366ce89324SYegor Yefremov 2376ce89324SYegor Yefremov void set_mux_conf_regs(void) 2386ce89324SYegor Yefremov { 2396ce89324SYegor Yefremov enable_board_pin_mux(); 2406ce89324SYegor Yefremov } 2416ce89324SYegor Yefremov 2426ce89324SYegor Yefremov const struct ctrl_ioregs ioregs_baltos = { 2436ce89324SYegor Yefremov .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 2446ce89324SYegor Yefremov .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 2456ce89324SYegor Yefremov .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 2466ce89324SYegor Yefremov .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 2476ce89324SYegor Yefremov .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE, 2486ce89324SYegor Yefremov }; 2496ce89324SYegor Yefremov 2506ce89324SYegor Yefremov void sdram_init(void) 2516ce89324SYegor Yefremov { 2526ce89324SYegor Yefremov gpio_request(GPIO_DDR_VTT_EN, "ddr_vtt_en"); 2536ce89324SYegor Yefremov gpio_direction_output(GPIO_DDR_VTT_EN, 1); 2546ce89324SYegor Yefremov 2556ce89324SYegor Yefremov config_ddr(400, &ioregs_baltos, 2566ce89324SYegor Yefremov &ddr3_baltos_data, 2576ce89324SYegor Yefremov &ddr3_baltos_cmd_ctrl_data, 2586ce89324SYegor Yefremov &ddr3_baltos_emif_reg_data, 0); 2596ce89324SYegor Yefremov } 2606ce89324SYegor Yefremov #endif 2616ce89324SYegor Yefremov 2626ce89324SYegor Yefremov /* 2636ce89324SYegor Yefremov * Basic board specific setup. Pinmux has been handled already. 2646ce89324SYegor Yefremov */ 2656ce89324SYegor Yefremov int board_init(void) 2666ce89324SYegor Yefremov { 2676ce89324SYegor Yefremov #if defined(CONFIG_HW_WATCHDOG) 2686ce89324SYegor Yefremov hw_watchdog_init(); 2696ce89324SYegor Yefremov #endif 2706ce89324SYegor Yefremov 2716ce89324SYegor Yefremov gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; 2726ce89324SYegor Yefremov #if defined(CONFIG_NOR) || defined(CONFIG_NAND) 2736ce89324SYegor Yefremov gpmc_init(); 2746ce89324SYegor Yefremov #endif 2756ce89324SYegor Yefremov return 0; 2766ce89324SYegor Yefremov } 2776ce89324SYegor Yefremov 2786ce89324SYegor Yefremov int ft_board_setup(void *blob, bd_t *bd) 2796ce89324SYegor Yefremov { 2806ce89324SYegor Yefremov int node, ret; 2816ce89324SYegor Yefremov unsigned char mac_addr[6]; 2826ce89324SYegor Yefremov BSP_VS_HWPARAM header; 2836ce89324SYegor Yefremov 2846ce89324SYegor Yefremov /* get production data */ 2856ce89324SYegor Yefremov if (read_eeprom(&header)) 2866ce89324SYegor Yefremov return 0; 2876ce89324SYegor Yefremov 2886ce89324SYegor Yefremov /* setup MAC1 */ 2896ce89324SYegor Yefremov mac_addr[0] = header.MAC1[0]; 2906ce89324SYegor Yefremov mac_addr[1] = header.MAC1[1]; 2916ce89324SYegor Yefremov mac_addr[2] = header.MAC1[2]; 2926ce89324SYegor Yefremov mac_addr[3] = header.MAC1[3]; 2936ce89324SYegor Yefremov mac_addr[4] = header.MAC1[4]; 2946ce89324SYegor Yefremov mac_addr[5] = header.MAC1[5]; 2956ce89324SYegor Yefremov 2966ce89324SYegor Yefremov 2976ce89324SYegor Yefremov node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100200"); 2986ce89324SYegor Yefremov if (node < 0) { 2996ce89324SYegor Yefremov printf("no /soc/fman/ethernet path offset\n"); 3006ce89324SYegor Yefremov return -ENODEV; 3016ce89324SYegor Yefremov } 3026ce89324SYegor Yefremov 3036ce89324SYegor Yefremov ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); 3046ce89324SYegor Yefremov if (ret) { 3056ce89324SYegor Yefremov printf("error setting local-mac-address property\n"); 3066ce89324SYegor Yefremov return -ENODEV; 3076ce89324SYegor Yefremov } 3086ce89324SYegor Yefremov 3096ce89324SYegor Yefremov /* setup MAC2 */ 3106ce89324SYegor Yefremov mac_addr[0] = header.MAC2[0]; 3116ce89324SYegor Yefremov mac_addr[1] = header.MAC2[1]; 3126ce89324SYegor Yefremov mac_addr[2] = header.MAC2[2]; 3136ce89324SYegor Yefremov mac_addr[3] = header.MAC2[3]; 3146ce89324SYegor Yefremov mac_addr[4] = header.MAC2[4]; 3156ce89324SYegor Yefremov mac_addr[5] = header.MAC2[5]; 3166ce89324SYegor Yefremov 3176ce89324SYegor Yefremov node = fdt_path_offset(blob, "/ocp/ethernet/slave@4a100300"); 3186ce89324SYegor Yefremov if (node < 0) { 3196ce89324SYegor Yefremov printf("no /soc/fman/ethernet path offset\n"); 3206ce89324SYegor Yefremov return -ENODEV; 3216ce89324SYegor Yefremov } 3226ce89324SYegor Yefremov 3236ce89324SYegor Yefremov ret = fdt_setprop(blob, node, "mac-address", &mac_addr, 6); 3246ce89324SYegor Yefremov if (ret) { 3256ce89324SYegor Yefremov printf("error setting local-mac-address property\n"); 3266ce89324SYegor Yefremov return -ENODEV; 3276ce89324SYegor Yefremov } 3286ce89324SYegor Yefremov 3296ce89324SYegor Yefremov printf("\nFDT was successfully setup\n"); 3306ce89324SYegor Yefremov 3316ce89324SYegor Yefremov return 0; 3326ce89324SYegor Yefremov } 3336ce89324SYegor Yefremov 334dcf7f6f1SYegor Yefremov static struct module_pin_mux pcie_sw_pin_mux[] = { 335dcf7f6f1SYegor Yefremov {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN )}, /* GPIO3_4 */ 336dcf7f6f1SYegor Yefremov {-1}, 337dcf7f6f1SYegor Yefremov }; 338dcf7f6f1SYegor Yefremov 3396ce89324SYegor Yefremov static struct module_pin_mux dip_pin_mux[] = { 3406ce89324SYegor Yefremov {OFFSET(gpmc_ad12), (MODE(7) | RXACTIVE )}, /* GPIO1_12 */ 3416ce89324SYegor Yefremov {OFFSET(gpmc_ad13), (MODE(7) | RXACTIVE )}, /* GPIO1_13 */ 3426ce89324SYegor Yefremov {OFFSET(gpmc_ad14), (MODE(7) | RXACTIVE )}, /* GPIO1_14 */ 3436ce89324SYegor Yefremov {OFFSET(gpmc_ad15), (MODE(7) | RXACTIVE )}, /* GPIO1_15 */ 3446ce89324SYegor Yefremov {-1}, 3456ce89324SYegor Yefremov }; 3466ce89324SYegor Yefremov 3476ce89324SYegor Yefremov #ifdef CONFIG_BOARD_LATE_INIT 3486ce89324SYegor Yefremov int board_late_init(void) 3496ce89324SYegor Yefremov { 3506ce89324SYegor Yefremov #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 3516ce89324SYegor Yefremov BSP_VS_HWPARAM header; 3526ce89324SYegor Yefremov char model[4]; 3536ce89324SYegor Yefremov 3546ce89324SYegor Yefremov /* get production data */ 3556ce89324SYegor Yefremov if (read_eeprom(&header)) { 356192bc694SBen Whitten strcpy(model, "211"); 3576ce89324SYegor Yefremov } else { 3586ce89324SYegor Yefremov sprintf(model, "%d", header.SystemId); 3596ce89324SYegor Yefremov if (header.SystemId == 215) { 3606ce89324SYegor Yefremov configure_module_pin_mux(dip_pin_mux); 3616ce89324SYegor Yefremov baltos_set_console(); 3626ce89324SYegor Yefremov } 3636ce89324SYegor Yefremov } 364dcf7f6f1SYegor Yefremov 365dcf7f6f1SYegor Yefremov /* turn power for the mPCIe slot */ 366dcf7f6f1SYegor Yefremov configure_module_pin_mux(pcie_sw_pin_mux); 367dcf7f6f1SYegor Yefremov if (gpio_request(MPCIE_SW, "mpcie_sw")) { 368dcf7f6f1SYegor Yefremov printf("failed to export GPIO %d\n", MPCIE_SW); 369dcf7f6f1SYegor Yefremov return -ENODEV; 370dcf7f6f1SYegor Yefremov } 371dcf7f6f1SYegor Yefremov if (gpio_direction_output(MPCIE_SW, 1)) { 372dcf7f6f1SYegor Yefremov printf("failed to set GPIO %d direction\n", MPCIE_SW); 373dcf7f6f1SYegor Yefremov return -ENODEV; 374dcf7f6f1SYegor Yefremov } 375dcf7f6f1SYegor Yefremov 376*382bee57SSimon Glass env_set("board_name", model); 3776ce89324SYegor Yefremov #endif 3786ce89324SYegor Yefremov 3796ce89324SYegor Yefremov return 0; 3806ce89324SYegor Yefremov } 3816ce89324SYegor Yefremov #endif 3826ce89324SYegor Yefremov 3836ce89324SYegor Yefremov #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 3846ce89324SYegor Yefremov (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 3856ce89324SYegor Yefremov static void cpsw_control(int enabled) 3866ce89324SYegor Yefremov { 3876ce89324SYegor Yefremov /* VTP can be added here */ 3886ce89324SYegor Yefremov 3896ce89324SYegor Yefremov return; 3906ce89324SYegor Yefremov } 3916ce89324SYegor Yefremov 3926ce89324SYegor Yefremov static struct cpsw_slave_data cpsw_slaves[] = { 3936ce89324SYegor Yefremov { 3946ce89324SYegor Yefremov .slave_reg_ofs = 0x208, 3956ce89324SYegor Yefremov .sliver_reg_ofs = 0xd80, 3966ce89324SYegor Yefremov .phy_addr = 0, 3976ce89324SYegor Yefremov }, 3986ce89324SYegor Yefremov { 3996ce89324SYegor Yefremov .slave_reg_ofs = 0x308, 4006ce89324SYegor Yefremov .sliver_reg_ofs = 0xdc0, 4016ce89324SYegor Yefremov .phy_addr = 7, 4026ce89324SYegor Yefremov }, 4036ce89324SYegor Yefremov }; 4046ce89324SYegor Yefremov 4056ce89324SYegor Yefremov static struct cpsw_platform_data cpsw_data = { 4066ce89324SYegor Yefremov .mdio_base = CPSW_MDIO_BASE, 4076ce89324SYegor Yefremov .cpsw_base = CPSW_BASE, 4086ce89324SYegor Yefremov .mdio_div = 0xff, 4096ce89324SYegor Yefremov .channels = 8, 4106ce89324SYegor Yefremov .cpdma_reg_ofs = 0x800, 4116ce89324SYegor Yefremov .slaves = 2, 4126ce89324SYegor Yefremov .slave_data = cpsw_slaves, 4136ce89324SYegor Yefremov .active_slave = 1, 4146ce89324SYegor Yefremov .ale_reg_ofs = 0xd00, 4156ce89324SYegor Yefremov .ale_entries = 1024, 4166ce89324SYegor Yefremov .host_port_reg_ofs = 0x108, 4176ce89324SYegor Yefremov .hw_stats_reg_ofs = 0x900, 4186ce89324SYegor Yefremov .bd_ram_ofs = 0x2000, 4196ce89324SYegor Yefremov .mac_control = (1 << 5), 4206ce89324SYegor Yefremov .control = cpsw_control, 4216ce89324SYegor Yefremov .host_port_num = 0, 4226ce89324SYegor Yefremov .version = CPSW_CTRL_VERSION_2, 4236ce89324SYegor Yefremov }; 4246ce89324SYegor Yefremov #endif 4256ce89324SYegor Yefremov 4266ce89324SYegor Yefremov #if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) \ 4276ce89324SYegor Yefremov && defined(CONFIG_SPL_BUILD)) || \ 4286ce89324SYegor Yefremov ((defined(CONFIG_DRIVER_TI_CPSW) || \ 42995de1e2fSPaul Kocialkowski defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)) && \ 4306ce89324SYegor Yefremov !defined(CONFIG_SPL_BUILD)) 4316ce89324SYegor Yefremov int board_eth_init(bd_t *bis) 4326ce89324SYegor Yefremov { 4336ce89324SYegor Yefremov int rv, n = 0; 4346ce89324SYegor Yefremov uint8_t mac_addr[6]; 4356ce89324SYegor Yefremov uint32_t mac_hi, mac_lo; 4366ce89324SYegor Yefremov 4376ce89324SYegor Yefremov /* 4386ce89324SYegor Yefremov * Note here that we're using CPSW1 since that has a 1Gbit PHY while 4396ce89324SYegor Yefremov * CSPW0 has a 100Mbit PHY. 4406ce89324SYegor Yefremov * 4416ce89324SYegor Yefremov * On product, CPSW1 maps to port labeled WAN. 4426ce89324SYegor Yefremov */ 4436ce89324SYegor Yefremov 4446ce89324SYegor Yefremov /* try reading mac address from efuse */ 4456ce89324SYegor Yefremov mac_lo = readl(&cdev->macid1l); 4466ce89324SYegor Yefremov mac_hi = readl(&cdev->macid1h); 4476ce89324SYegor Yefremov mac_addr[0] = mac_hi & 0xFF; 4486ce89324SYegor Yefremov mac_addr[1] = (mac_hi & 0xFF00) >> 8; 4496ce89324SYegor Yefremov mac_addr[2] = (mac_hi & 0xFF0000) >> 16; 4506ce89324SYegor Yefremov mac_addr[3] = (mac_hi & 0xFF000000) >> 24; 4516ce89324SYegor Yefremov mac_addr[4] = mac_lo & 0xFF; 4526ce89324SYegor Yefremov mac_addr[5] = (mac_lo & 0xFF00) >> 8; 4536ce89324SYegor Yefremov 4546ce89324SYegor Yefremov #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \ 4556ce89324SYegor Yefremov (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD)) 4566ce89324SYegor Yefremov if (!getenv("ethaddr")) { 4576ce89324SYegor Yefremov printf("<ethaddr> not set. Validating first E-fuse MAC\n"); 4586ce89324SYegor Yefremov 4596ce89324SYegor Yefremov if (is_valid_ethaddr(mac_addr)) 4606ce89324SYegor Yefremov eth_setenv_enetaddr("ethaddr", mac_addr); 4616ce89324SYegor Yefremov } 4626ce89324SYegor Yefremov 4636ce89324SYegor Yefremov #ifdef CONFIG_DRIVER_TI_CPSW 4646ce89324SYegor Yefremov writel((GMII1_SEL_RMII | GMII2_SEL_RGMII | RGMII2_IDMODE), &cdev->miisel); 4656ce89324SYegor Yefremov cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RGMII; 4666ce89324SYegor Yefremov rv = cpsw_register(&cpsw_data); 4676ce89324SYegor Yefremov if (rv < 0) 4686ce89324SYegor Yefremov printf("Error %d registering CPSW switch\n", rv); 4696ce89324SYegor Yefremov else 4706ce89324SYegor Yefremov n += rv; 4716ce89324SYegor Yefremov #endif 4726ce89324SYegor Yefremov 4736ce89324SYegor Yefremov /* 4746ce89324SYegor Yefremov * 4756ce89324SYegor Yefremov * CPSW RGMII Internal Delay Mode is not supported in all PVT 4766ce89324SYegor Yefremov * operating points. So we must set the TX clock delay feature 4776ce89324SYegor Yefremov * in the AR8051 PHY. Since we only support a single ethernet 4786ce89324SYegor Yefremov * device in U-Boot, we only do this for the first instance. 4796ce89324SYegor Yefremov */ 4806ce89324SYegor Yefremov #define AR8051_PHY_DEBUG_ADDR_REG 0x1d 4816ce89324SYegor Yefremov #define AR8051_PHY_DEBUG_DATA_REG 0x1e 4826ce89324SYegor Yefremov #define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5 4836ce89324SYegor Yefremov #define AR8051_RGMII_TX_CLK_DLY 0x100 4846ce89324SYegor Yefremov const char *devname; 4856ce89324SYegor Yefremov devname = miiphy_get_current_dev(); 4866ce89324SYegor Yefremov 4876ce89324SYegor Yefremov miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_ADDR_REG, 4886ce89324SYegor Yefremov AR8051_DEBUG_RGMII_CLK_DLY_REG); 4896ce89324SYegor Yefremov miiphy_write(devname, 0x7, AR8051_PHY_DEBUG_DATA_REG, 4906ce89324SYegor Yefremov AR8051_RGMII_TX_CLK_DLY); 4916ce89324SYegor Yefremov #endif 4926ce89324SYegor Yefremov return n; 4936ce89324SYegor Yefremov } 4946ce89324SYegor Yefremov #endif 495