xref: /openbmc/u-boot/board/ve8313/ve8313.c (revision 5994e8b6)
1 /*
2  * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
3  *
4  * Author: Scott Wood <scottwood@freescale.com>
5  *
6  * (C) Copyright 2010
7  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
8  *
9  * SPDX-License-Identifier:	GPL-2.0+
10  */
11 
12 #include <common.h>
13 #include <libfdt.h>
14 #include <pci.h>
15 #include <mpc83xx.h>
16 #include <ns16550.h>
17 #include <nand.h>
18 
19 #include <asm/bitops.h>
20 #include <asm/io.h>
21 
22 DECLARE_GLOBAL_DATA_PTR;
23 
24 extern void disable_addr_trans (void);
25 extern void enable_addr_trans (void);
26 
27 int checkboard(void)
28 {
29 	puts("Board: ve8313\n");
30 	return 0;
31 }
32 
33 static long fixed_sdram(void)
34 {
35 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
36 
37 #ifndef CONFIG_SYS_RAMBOOT
38 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
39 	u32 msize_log2 = __ilog2(msize);
40 
41 	out_be32(&im->sysconf.ddrlaw[0].bar,
42 		(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
43 	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
44 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
45 
46 	/*
47 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
48 	 * or the DDR2 controller may fail to initialize correctly.
49 	 */
50 	__udelay(50000);
51 
52 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
53 #warning Chip select bounds is only configurable in 16MB increments
54 #endif
55 	out_be32(&im->ddr.csbnds[0].csbnds,
56 		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
57 		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
58 			CSBNDS_EA));
59 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
60 
61 	/* Currently we use only one CS, so disable the other bank. */
62 	out_be32(&im->ddr.cs_config[1], 0);
63 
64 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
65 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
66 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
67 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
68 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
69 
70 	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
71 
72 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
73 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
74 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
75 
76 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
77 	sync();
78 
79 	/* enable DDR controller */
80 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
81 
82 	/* now check the real size */
83 	disable_addr_trans ();
84 	msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
85 	enable_addr_trans ();
86 #endif
87 
88 	return msize;
89 }
90 
91 int dram_init(void)
92 {
93 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
94 	volatile fsl_lbc_t *lbc = &im->im_lbc;
95 	u32 msize;
96 
97 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
98 		return -1;
99 
100 	/* DDR SDRAM - Main SODIMM */
101 	msize = fixed_sdram();
102 
103 	/* Local Bus setup lbcr and mrtpr */
104 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
105 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
106 	sync();
107 
108 	/* return total bus SDRAM size(bytes)  -- DDR */
109 	gd->ram_size = msize;
110 
111 	return 0;
112 }
113 
114 #define VE8313_WDT_EN	0x00020000
115 #define VE8313_WDT_TRIG	0x00040000
116 
117 int board_early_init_f (void)
118 {
119 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
120 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
121 
122 #if defined(CONFIG_HW_WATCHDOG)
123 	/* enable WDT */
124 	clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
125 #else
126 	/* disable WDT */
127 	setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
128 #endif
129 	/* set WDT pins as output */
130 	setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
131 
132 	return 0;
133 }
134 
135 #if defined(CONFIG_HW_WATCHDOG)
136 void hw_watchdog_reset(void)
137 {
138 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
139 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
140 	unsigned long reg;
141 
142 	reg = in_be32(&gpio->dat);
143 	if (reg & VE8313_WDT_TRIG)
144 		clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
145 	else
146 		setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
147 }
148 #endif
149 
150 
151 #if defined(CONFIG_PCI)
152 static struct pci_region pci_regions[] = {
153 	{
154 		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
155 		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
156 		size: CONFIG_SYS_PCI1_MEM_SIZE,
157 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
158 	},
159 	{
160 		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
161 		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
162 		size: CONFIG_SYS_PCI1_MMIO_SIZE,
163 		flags: PCI_REGION_MEM
164 	},
165 	{
166 		bus_start: CONFIG_SYS_PCI1_IO_BASE,
167 		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
168 		size: CONFIG_SYS_PCI1_IO_SIZE,
169 		flags: PCI_REGION_IO
170 	}
171 };
172 
173 void pci_init_board(void)
174 {
175 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
176 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
177 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
178 	struct pci_region *reg[] = { pci_regions };
179 
180 	/* Enable all 3 PCI_CLK_OUTPUTs. */
181 	setbits_be32(&clk->occr, 0xe0000000);
182 
183 	/*
184 	 * Configure PCI Local Access Windows
185 	 */
186 	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
187 	out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
188 
189 	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
190 	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
191 
192 	mpc83xx_pci_init(1, reg);
193 }
194 #endif
195 
196 #if defined(CONFIG_OF_BOARD_SETUP)
197 int ft_board_setup(void *blob, bd_t *bd)
198 {
199 	ft_cpu_setup(blob, bd);
200 #ifdef CONFIG_PCI
201 	ft_pci_setup(blob, bd);
202 #endif
203 
204 	return 0;
205 }
206 #endif
207