xref: /openbmc/u-boot/board/ve8313/ve8313.c (revision 3ba98ed8)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) Freescale Semiconductor, Inc. 2006-2007
4  *
5  * Author: Scott Wood <scottwood@freescale.com>
6  *
7  * (C) Copyright 2010
8  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
9  */
10 
11 #include <common.h>
12 #include <linux/libfdt.h>
13 #include <pci.h>
14 #include <mpc83xx.h>
15 #include <ns16550.h>
16 #include <nand.h>
17 
18 #include <asm/bitops.h>
19 #include <asm/io.h>
20 
21 DECLARE_GLOBAL_DATA_PTR;
22 
23 extern void disable_addr_trans (void);
24 extern void enable_addr_trans (void);
25 
26 int checkboard(void)
27 {
28 	puts("Board: ve8313\n");
29 	return 0;
30 }
31 
32 static long fixed_sdram(void)
33 {
34 	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
35 
36 #ifndef CONFIG_SYS_RAMBOOT
37 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
38 	u32 msize_log2 = __ilog2(msize);
39 
40 	out_be32(&im->sysconf.ddrlaw[0].bar,
41 		(CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
42 	out_be32(&im->sysconf.ddrlaw[0].ar, (LBLAWAR_EN | (msize_log2 - 1)));
43 	out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
44 
45 	/*
46 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
47 	 * or the DDR2 controller may fail to initialize correctly.
48 	 */
49 	__udelay(50000);
50 
51 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
52 #warning Chip select bounds is only configurable in 16MB increments
53 #endif
54 	out_be32(&im->ddr.csbnds[0].csbnds,
55 		((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
56 		(((CONFIG_SYS_DDR_SDRAM_BASE + msize - 1) >> CSBNDS_EA_SHIFT) &
57 			CSBNDS_EA));
58 	out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
59 
60 	/* Currently we use only one CS, so disable the other bank. */
61 	out_be32(&im->ddr.cs_config[1], 0);
62 
63 	out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
64 	out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
65 	out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
66 	out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
67 	out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
68 
69 	out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
70 
71 	out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
72 	out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
73 	out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
74 
75 	out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
76 	sync();
77 
78 	/* enable DDR controller */
79 	setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
80 
81 	/* now check the real size */
82 	disable_addr_trans ();
83 	msize = get_ram_size (CONFIG_SYS_DDR_BASE, msize);
84 	enable_addr_trans ();
85 #endif
86 
87 	return msize;
88 }
89 
90 int dram_init(void)
91 {
92 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
93 	volatile fsl_lbc_t *lbc = &im->im_lbc;
94 	u32 msize;
95 
96 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
97 		return -1;
98 
99 	/* DDR SDRAM - Main SODIMM */
100 	msize = fixed_sdram();
101 
102 	/* Local Bus setup lbcr and mrtpr */
103 	out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
104 	out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
105 	sync();
106 
107 	/* return total bus SDRAM size(bytes)  -- DDR */
108 	gd->ram_size = msize;
109 
110 	return 0;
111 }
112 
113 #define VE8313_WDT_EN	0x00020000
114 #define VE8313_WDT_TRIG	0x00040000
115 
116 int board_early_init_f (void)
117 {
118 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
119 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
120 
121 #if defined(CONFIG_HW_WATCHDOG)
122 	/* enable WDT */
123 	clrbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
124 #else
125 	/* disable WDT */
126 	setbits_be32(&gpio->dat, VE8313_WDT_EN | VE8313_WDT_TRIG);
127 #endif
128 	/* set WDT pins as output */
129 	setbits_be32(&gpio->dir, VE8313_WDT_EN | VE8313_WDT_TRIG);
130 
131 	return 0;
132 }
133 
134 #if defined(CONFIG_HW_WATCHDOG)
135 void hw_watchdog_reset(void)
136 {
137 	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
138 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)im->gpio;
139 	unsigned long reg;
140 
141 	reg = in_be32(&gpio->dat);
142 	if (reg & VE8313_WDT_TRIG)
143 		clrbits_be32(&gpio->dat, VE8313_WDT_TRIG);
144 	else
145 		setbits_be32(&gpio->dat, VE8313_WDT_TRIG);
146 }
147 #endif
148 
149 
150 #if defined(CONFIG_PCI)
151 static struct pci_region pci_regions[] = {
152 	{
153 		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
154 		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
155 		size: CONFIG_SYS_PCI1_MEM_SIZE,
156 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
157 	},
158 	{
159 		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
160 		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
161 		size: CONFIG_SYS_PCI1_MMIO_SIZE,
162 		flags: PCI_REGION_MEM
163 	},
164 	{
165 		bus_start: CONFIG_SYS_PCI1_IO_BASE,
166 		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
167 		size: CONFIG_SYS_PCI1_IO_SIZE,
168 		flags: PCI_REGION_IO
169 	}
170 };
171 
172 void pci_init_board(void)
173 {
174 	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
175 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
176 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
177 	struct pci_region *reg[] = { pci_regions };
178 
179 	/* Enable all 3 PCI_CLK_OUTPUTs. */
180 	setbits_be32(&clk->occr, 0xe0000000);
181 
182 	/*
183 	 * Configure PCI Local Access Windows
184 	 */
185 	out_be32(&pci_law[0].bar, CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR);
186 	out_be32(&pci_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
187 
188 	out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR);
189 	out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB);
190 
191 	mpc83xx_pci_init(1, reg);
192 }
193 #endif
194 
195 #if defined(CONFIG_OF_BOARD_SETUP)
196 int ft_board_setup(void *blob, bd_t *bd)
197 {
198 	ft_cpu_setup(blob, bd);
199 #ifdef CONFIG_PCI
200 	ft_pci_setup(blob, bd);
201 #endif
202 
203 	return 0;
204 }
205 #endif
206