1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Author Adrian Cox 4 * Based somewhat on board/freescale/corenet_ds/eth_hydra.c 5 */ 6 7 #include <common.h> 8 #include <netdev.h> 9 #include <asm/fsl_serdes.h> 10 #include <fm_eth.h> 11 #include <fsl_mdio.h> 12 #include <malloc.h> 13 #include <fdt_support.h> 14 #include <fsl_dtsec.h> 15 16 #ifdef CONFIG_FMAN_ENET 17 18 #define FIRST_PORT_ADDR 3 19 #define SECOND_PORT_ADDR 7 20 21 #ifdef CONFIG_ARCH_P5040 22 #define FIRST_PORT FM1_DTSEC5 23 #define SECOND_PORT FM2_DTSEC5 24 #else 25 #define FIRST_PORT FM1_DTSEC4 26 #define SECOND_PORT FM1_DTSEC5 27 #endif 28 29 #define IS_VALID_PORT(p) ((p) == FIRST_PORT || (p) == SECOND_PORT) 30 31 static void cyrus_phy_tuning(int phy) 32 { 33 /* 34 * Enable RGMII delay on Tx and Rx for CPU port 35 */ 36 printf("Tuning PHY @ %d\n", phy); 37 38 /* sets address 0x104 or reg 260 for writing */ 39 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8104); 40 /* Sets RXC/TXC to +0.96ns and TX_CTL/RX_CTL to -0.84ns */ 41 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0xf0f0); 42 /* sets address 0x105 or reg 261 for writing */ 43 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8105); 44 /* writes to address 0x105 , RXD[3..0] to -0. */ 45 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); 46 /* sets address 0x106 or reg 261 for writing */ 47 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xb, 0x8106); 48 /* writes to address 0x106 , TXD[3..0] to -0.84ns */ 49 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0xc, 0x0000); 50 /* force re-negotiation */ 51 miiphy_write(DEFAULT_FM_MDIO_NAME, phy, 0x0, 0x1340); 52 } 53 #endif 54 55 int board_eth_init(bd_t *bis) 56 { 57 #ifdef CONFIG_FMAN_ENET 58 struct fsl_pq_mdio_info dtsec_mdio_info; 59 unsigned int i; 60 61 printf("Initializing Fman\n"); 62 63 64 /* Register the real 1G MDIO bus */ 65 dtsec_mdio_info.regs = 66 (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; 67 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; 68 69 fsl_pq_mdio_init(bis, &dtsec_mdio_info); 70 71 72 fm_info_set_phy_address(FIRST_PORT, FIRST_PORT_ADDR); 73 fm_info_set_mdio(FIRST_PORT, 74 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); 75 fm_info_set_phy_address(SECOND_PORT, SECOND_PORT_ADDR); 76 fm_info_set_mdio(SECOND_PORT, 77 miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME)); 78 79 /* Never disable DTSEC1 - it controls MDIO */ 80 for (i = FM1_DTSEC2; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { 81 if (!IS_VALID_PORT(i)) 82 fm_disable_port(i); 83 } 84 85 #ifdef CONFIG_ARCH_P5040 86 for (i = FM2_DTSEC2; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { 87 if (!IS_VALID_PORT(i)) 88 fm_disable_port(i); 89 } 90 #endif 91 92 cpu_eth_init(bis); 93 94 cyrus_phy_tuning(FIRST_PORT_ADDR); 95 cyrus_phy_tuning(SECOND_PORT_ADDR); 96 #endif 97 98 return pci_eth_init(bis); 99 } 100