1 /* 2 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 3 * Copyright (C) Jasbir Matharu 4 * Copyright (C) UDOO Team 5 * 6 * Author: Breno Lima <breno.lima@nxp.com> 7 * Author: Francesco Montefoschi <francesco.monte@gmail.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <asm/arch/clock.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/iomux.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/iomux-v3.h> 18 #include <mmc.h> 19 #include <fsl_esdhc.h> 20 #include <asm/arch/crm_regs.h> 21 #include <asm/io.h> 22 #include <asm/arch/sys_proto.h> 23 #include <spl.h> 24 #include <linux/sizes.h> 25 #include <common.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 enum { 30 UDOO_NEO_TYPE_BASIC, 31 UDOO_NEO_TYPE_BASIC_KS, 32 UDOO_NEO_TYPE_FULL, 33 UDOO_NEO_TYPE_EXTENDED, 34 }; 35 36 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 41 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 42 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 44 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ 45 PAD_CTL_DSE_40ohm) 46 47 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 48 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 49 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 50 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ 51 MUX_MODE_SION) 52 53 int dram_init(void) 54 { 55 gd->ram_size = imx_ddr_size(); 56 return 0; 57 } 58 59 static iomux_v3_cfg_t const uart1_pads[] = { 60 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 61 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 62 }; 63 64 static iomux_v3_cfg_t const usdhc2_pads[] = { 65 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 /* CD pin */ 72 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), 73 /* Power */ 74 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), 75 }; 76 77 static iomux_v3_cfg_t const board_recognition_pads[] = { 78 /*Connected to R184*/ 79 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, 80 /*Connected to R185*/ 81 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, 82 }; 83 84 static iomux_v3_cfg_t const wdog_b_pad = { 85 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), 86 }; 87 88 static iomux_v3_cfg_t const peri_3v3_pads[] = { 89 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 90 }; 91 92 static void setup_iomux_uart(void) 93 { 94 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 95 } 96 97 int board_init(void) 98 { 99 /* Address of boot parameters */ 100 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 101 102 /* 103 * Because kernel set WDOG_B mux before pad with the commone pinctrl 104 * framwork now and wdog reset will be triggered once set WDOG_B mux 105 * with default pad setting, we set pad setting here to workaround this. 106 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set 107 * as GPIO mux firstly here to workaround it. 108 */ 109 imx_iomux_v3_setup_pad(wdog_b_pad); 110 111 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 112 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, 113 ARRAY_SIZE(peri_3v3_pads)); 114 115 /* Active high for ncp692 */ 116 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); 117 118 return 0; 119 } 120 121 static int get_board_value(void) 122 { 123 int r184, r185; 124 125 imx_iomux_v3_setup_multiple_pads(board_recognition_pads, 126 ARRAY_SIZE(board_recognition_pads)); 127 128 gpio_direction_input(IMX_GPIO_NR(4, 13)); 129 gpio_direction_input(IMX_GPIO_NR(4, 0)); 130 131 r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); 132 r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); 133 134 /* 135 * Machine selection - 136 * Machine r184, r185 137 * --------------------------------- 138 * Basic 0 0 139 * Basic Ks 0 1 140 * Full 1 0 141 * Extended 1 1 142 */ 143 144 return (r184 << 1) + r185; 145 } 146 147 int board_early_init_f(void) 148 { 149 setup_iomux_uart(); 150 151 return 0; 152 } 153 154 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 155 {USDHC2_BASE_ADDR, 0, 4}, 156 {USDHC3_BASE_ADDR, 0, 4}, 157 }; 158 159 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) 160 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) 161 162 int board_mmc_getcd(struct mmc *mmc) 163 { 164 return !gpio_get_value(USDHC2_CD_GPIO); 165 } 166 167 int board_mmc_init(bd_t *bis) 168 { 169 imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 170 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 171 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 172 gpio_direction_input(USDHC2_CD_GPIO); 173 gpio_direction_output(USDHC2_PWR_GPIO, 1); 174 175 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 176 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 177 } 178 179 char *board_string(void) 180 { 181 switch (get_board_value()) { 182 case UDOO_NEO_TYPE_BASIC: 183 return "BASIC"; 184 case UDOO_NEO_TYPE_BASIC_KS: 185 return "BASICKS"; 186 case UDOO_NEO_TYPE_FULL: 187 return "FULL"; 188 case UDOO_NEO_TYPE_EXTENDED: 189 return "EXTENDED"; 190 } 191 return "UNDEFINED"; 192 } 193 194 int checkboard(void) 195 { 196 printf("Board: UDOO Neo %s\n", board_string()); 197 return 0; 198 } 199 200 int board_late_init(void) 201 { 202 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 203 setenv("board_name", board_string()); 204 #endif 205 206 return 0; 207 } 208 209 #ifdef CONFIG_SPL_BUILD 210 211 #include <libfdt.h> 212 #include <asm/arch/mx6-ddr.h> 213 214 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { 215 .dram_dqm0 = 0x00000028, 216 .dram_dqm1 = 0x00000028, 217 .dram_dqm2 = 0x00000028, 218 .dram_dqm3 = 0x00000028, 219 .dram_ras = 0x00000020, 220 .dram_cas = 0x00000020, 221 .dram_odt0 = 0x00000020, 222 .dram_odt1 = 0x00000020, 223 .dram_sdba2 = 0x00000000, 224 .dram_sdcke0 = 0x00003000, 225 .dram_sdcke1 = 0x00003000, 226 .dram_sdclk_0 = 0x00000030, 227 .dram_sdqs0 = 0x00000028, 228 .dram_sdqs1 = 0x00000028, 229 .dram_sdqs2 = 0x00000028, 230 .dram_sdqs3 = 0x00000028, 231 .dram_reset = 0x00000020, 232 }; 233 234 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { 235 .grp_addds = 0x00000020, 236 .grp_ddrmode_ctl = 0x00020000, 237 .grp_ddrpke = 0x00000000, 238 .grp_ddrmode = 0x00020000, 239 .grp_b0ds = 0x00000028, 240 .grp_b1ds = 0x00000028, 241 .grp_ctlds = 0x00000020, 242 .grp_ddr_type = 0x000c0000, 243 .grp_b2ds = 0x00000028, 244 .grp_b3ds = 0x00000028, 245 }; 246 247 static const struct mx6_mmdc_calibration neo_mmcd_calib = { 248 .p0_mpwldectrl0 = 0x000E000B, 249 .p0_mpwldectrl1 = 0x000E0010, 250 .p0_mpdgctrl0 = 0x41600158, 251 .p0_mpdgctrl1 = 0x01500140, 252 .p0_mprddlctl = 0x3A383E3E, 253 .p0_mpwrdlctl = 0x3A383C38, 254 }; 255 256 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { 257 .p0_mpwldectrl0 = 0x001E0022, 258 .p0_mpwldectrl1 = 0x001C0019, 259 .p0_mpdgctrl0 = 0x41540150, 260 .p0_mpdgctrl1 = 0x01440138, 261 .p0_mprddlctl = 0x403E4644, 262 .p0_mpwrdlctl = 0x3C3A4038, 263 }; 264 265 /* MT41K256M16 */ 266 static struct mx6_ddr3_cfg neo_mem_ddr = { 267 .mem_speed = 1600, 268 .density = 4, 269 .width = 16, 270 .banks = 8, 271 .rowaddr = 15, 272 .coladdr = 10, 273 .pagesz = 2, 274 .trcd = 1375, 275 .trcmin = 4875, 276 .trasmin = 3500, 277 }; 278 279 /* MT41K128M16 */ 280 static struct mx6_ddr3_cfg neo_basic_mem_ddr = { 281 .mem_speed = 1600, 282 .density = 2, 283 .width = 16, 284 .banks = 8, 285 .rowaddr = 14, 286 .coladdr = 10, 287 .pagesz = 2, 288 .trcd = 1375, 289 .trcmin = 4875, 290 .trasmin = 3500, 291 }; 292 293 static void ccgr_init(void) 294 { 295 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 296 297 writel(0xFFFFFFFF, &ccm->CCGR0); 298 writel(0xFFFFFFFF, &ccm->CCGR1); 299 writel(0xFFFFFFFF, &ccm->CCGR2); 300 writel(0xFFFFFFFF, &ccm->CCGR3); 301 writel(0xFFFFFFFF, &ccm->CCGR4); 302 writel(0xFFFFFFFF, &ccm->CCGR5); 303 writel(0xFFFFFFFF, &ccm->CCGR6); 304 writel(0xFFFFFFFF, &ccm->CCGR7); 305 } 306 307 static void spl_dram_init(void) 308 { 309 int board = get_board_value(); 310 311 struct mx6_ddr_sysinfo sysinfo = { 312 .dsize = 1, /* width of data bus: 1 = 32 bits */ 313 .cs_density = 24, 314 .ncs = 1, 315 .cs1_mirror = 0, 316 .rtt_wr = 2, 317 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 318 .walat = 1, /* Write additional latency */ 319 .ralat = 5, /* Read additional latency */ 320 .mif3_mode = 3, /* Command prediction working mode */ 321 .bi_on = 1, /* Bank interleaving enabled */ 322 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 323 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 324 }; 325 326 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); 327 if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) 328 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, 329 &neo_basic_mem_ddr); 330 else 331 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); 332 } 333 334 void board_init_f(ulong dummy) 335 { 336 ccgr_init(); 337 338 /* setup AIPS and disable watchdog */ 339 arch_cpu_init(); 340 341 board_early_init_f(); 342 343 /* setup GP timer */ 344 timer_init(); 345 346 /* UART clocks enabled and gd valid - init serial console */ 347 preloader_console_init(); 348 349 /* DDR initialization */ 350 spl_dram_init(); 351 352 /* Clear the BSS. */ 353 memset(__bss_start, 0, __bss_end - __bss_start); 354 355 /* load/boot image from boot device */ 356 board_init_r(NULL, 0); 357 } 358 359 #endif 360