1 /* 2 * Copyright (C) 2014-2015 Freescale Semiconductor, Inc. 3 * Copyright (C) Jasbir Matharu 4 * Copyright (C) UDOO Team 5 * 6 * Author: Breno Lima <breno.lima@nxp.com> 7 * Author: Francesco Montefoschi <francesco.monte@gmail.com> 8 * 9 * SPDX-License-Identifier: GPL-2.0+ 10 */ 11 12 #include <asm/arch/clock.h> 13 #include <asm/arch/imx-regs.h> 14 #include <asm/arch/iomux.h> 15 #include <asm/arch/mx6-pins.h> 16 #include <asm/gpio.h> 17 #include <asm/imx-common/iomux-v3.h> 18 #include <mmc.h> 19 #include <fsl_esdhc.h> 20 #include <asm/arch/crm_regs.h> 21 #include <asm/io.h> 22 #include <asm/arch/sys_proto.h> 23 #include <spl.h> 24 #include <linux/sizes.h> 25 #include <common.h> 26 27 DECLARE_GLOBAL_DATA_PTR; 28 29 enum { 30 UDOO_NEO_TYPE_BASIC, 31 UDOO_NEO_TYPE_BASIC_KS, 32 UDOO_NEO_TYPE_FULL, 33 UDOO_NEO_TYPE_EXTENDED, 34 }; 35 36 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 37 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 38 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 39 40 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 41 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \ 42 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 43 44 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \ 45 PAD_CTL_DSE_40ohm) 46 47 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ 48 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 49 PAD_CTL_DSE_34ohm | PAD_CTL_HYS | PAD_CTL_SRE_FAST) 50 #define BOARD_DETECT_PAD_CFG (MUX_PAD_CTRL(BOARD_DETECT_PAD_CTRL) | \ 51 MUX_MODE_SION) 52 53 int dram_init(void) 54 { 55 gd->ram_size = imx_ddr_size(); 56 return 0; 57 } 58 59 static iomux_v3_cfg_t const uart1_pads[] = { 60 MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 61 MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 62 }; 63 64 static iomux_v3_cfg_t const usdhc2_pads[] = { 65 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 MX6_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX6_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX6_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 MX6_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 /* CD pin */ 72 MX6_PAD_SD1_DATA0__GPIO6_IO_2 | MUX_PAD_CTRL(NO_PAD_CTRL), 73 /* Power */ 74 MX6_PAD_SD1_CMD__GPIO6_IO_1 | MUX_PAD_CTRL(NO_PAD_CTRL), 75 }; 76 77 static iomux_v3_cfg_t const board_recognition_pads[] = { 78 /*Connected to R184*/ 79 MX6_PAD_NAND_READY_B__GPIO4_IO_13 | BOARD_DETECT_PAD_CFG, 80 /*Connected to R185*/ 81 MX6_PAD_NAND_ALE__GPIO4_IO_0 | BOARD_DETECT_PAD_CFG, 82 }; 83 84 static iomux_v3_cfg_t const usdhc3_pads[] = { 85 /* Configured for WLAN */ 86 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 87 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 88 MX6_PAD_SD3_DATA0__USDHC3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 89 MX6_PAD_SD3_DATA1__USDHC3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 90 MX6_PAD_SD3_DATA2__USDHC3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 91 MX6_PAD_SD3_DATA3__USDHC3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 92 }; 93 94 static iomux_v3_cfg_t const wdog_b_pad = { 95 MX6_PAD_GPIO1_IO13__GPIO1_IO_13 | MUX_PAD_CTRL(WDOG_PAD_CTRL), 96 }; 97 98 static iomux_v3_cfg_t const peri_3v3_pads[] = { 99 MX6_PAD_QSPI1A_DATA0__GPIO4_IO_16 | MUX_PAD_CTRL(NO_PAD_CTRL), 100 }; 101 102 static void setup_iomux_uart(void) 103 { 104 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 105 } 106 107 int board_init(void) 108 { 109 /* Address of boot parameters */ 110 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 111 112 /* 113 * Because kernel set WDOG_B mux before pad with the commone pinctrl 114 * framwork now and wdog reset will be triggered once set WDOG_B mux 115 * with default pad setting, we set pad setting here to workaround this. 116 * Since imx_iomux_v3_setup_pad also set mux before pad setting, we set 117 * as GPIO mux firstly here to workaround it. 118 */ 119 imx_iomux_v3_setup_pad(wdog_b_pad); 120 121 /* Enable PERI_3V3, which is used by SD2, ENET, LVDS, BT */ 122 imx_iomux_v3_setup_multiple_pads(peri_3v3_pads, 123 ARRAY_SIZE(peri_3v3_pads)); 124 125 /* Active high for ncp692 */ 126 gpio_direction_output(IMX_GPIO_NR(4, 16) , 1); 127 128 return 0; 129 } 130 131 static int get_board_value(void) 132 { 133 int r184, r185; 134 135 imx_iomux_v3_setup_multiple_pads(board_recognition_pads, 136 ARRAY_SIZE(board_recognition_pads)); 137 138 gpio_direction_input(IMX_GPIO_NR(4, 13)); 139 gpio_direction_input(IMX_GPIO_NR(4, 0)); 140 141 r184 = gpio_get_value(IMX_GPIO_NR(4, 13)); 142 r185 = gpio_get_value(IMX_GPIO_NR(4, 0)); 143 144 /* 145 * Machine selection - 146 * Machine r184, r185 147 * --------------------------------- 148 * Basic 0 0 149 * Basic Ks 0 1 150 * Full 1 0 151 * Extended 1 1 152 */ 153 154 return (r184 << 1) + r185; 155 } 156 157 int board_early_init_f(void) 158 { 159 setup_iomux_uart(); 160 161 return 0; 162 } 163 164 static struct fsl_esdhc_cfg usdhc_cfg[2] = { 165 {USDHC2_BASE_ADDR, 0, 4}, 166 {USDHC3_BASE_ADDR, 0, 4}, 167 }; 168 169 #define USDHC2_PWR_GPIO IMX_GPIO_NR(6, 1) 170 #define USDHC2_CD_GPIO IMX_GPIO_NR(6, 2) 171 172 int board_mmc_getcd(struct mmc *mmc) 173 { 174 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 175 int ret = 0; 176 177 switch (cfg->esdhc_base) { 178 case USDHC2_BASE_ADDR: 179 ret = !gpio_get_value(USDHC2_CD_GPIO); 180 break; 181 } 182 183 return ret; 184 } 185 186 int board_mmc_init(bd_t *bis) 187 { 188 #ifndef CONFIG_SPL_BUILD 189 int i, ret; 190 191 /* 192 * According to the board_mmc_init() the following map is done: 193 * (U-boot device node) (Physical Port) 194 * mmc0 USDHC2 195 */ 196 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 197 switch (i) { 198 case 0: 199 imx_iomux_v3_setup_multiple_pads( 200 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 201 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 202 gpio_direction_input(USDHC2_CD_GPIO); 203 gpio_direction_output(USDHC2_PWR_GPIO, 1); 204 break; 205 case 1: 206 imx_iomux_v3_setup_multiple_pads( 207 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 208 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 209 break; 210 default: 211 printf("Warning: you configured more USDHC controllers\ 212 (%d) than supported by the board\n", i + 1); 213 return -EINVAL; 214 } 215 216 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 217 if (ret) { 218 printf("Warning:\ 219 failed to initialize mmc dev %d\n", i); 220 return ret; 221 } 222 } 223 224 return 0; 225 #else 226 struct src *src_regs = (struct src *)SRC_BASE_ADDR; 227 u32 val; 228 u32 port; 229 230 val = readl(&src_regs->sbmr1); 231 232 if ((val & 0xc0) != 0x40) { 233 printf("Not boot from USDHC!\n"); 234 return -EINVAL; 235 } 236 237 port = (val >> 11) & 0x3; 238 printf("port %d\n", port); 239 switch (port) { 240 case 1: 241 imx_iomux_v3_setup_multiple_pads( 242 usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); 243 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 244 usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; 245 gpio_direction_input(USDHC2_CD_GPIO); 246 gpio_direction_output(USDHC2_PWR_GPIO, 1); 247 break; 248 case 2: 249 imx_iomux_v3_setup_multiple_pads( 250 usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); 251 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); 252 usdhc_cfg[1].esdhc_base = USDHC3_BASE_ADDR; 253 break; 254 } 255 256 gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; 257 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); 258 #endif 259 } 260 261 char *board_string(void) 262 { 263 switch (get_board_value()) { 264 case UDOO_NEO_TYPE_BASIC: 265 return "BASIC"; 266 case UDOO_NEO_TYPE_BASIC_KS: 267 return "BASICKS"; 268 case UDOO_NEO_TYPE_FULL: 269 return "FULL"; 270 case UDOO_NEO_TYPE_EXTENDED: 271 return "EXTENDED"; 272 } 273 return "UNDEFINED"; 274 } 275 276 int checkboard(void) 277 { 278 printf("Board: UDOO Neo %s\n", board_string()); 279 return 0; 280 } 281 282 int board_late_init(void) 283 { 284 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 285 setenv("board_name", board_string()); 286 #endif 287 288 return 0; 289 } 290 291 #ifdef CONFIG_SPL_BUILD 292 293 #include <libfdt.h> 294 #include <asm/arch/mx6-ddr.h> 295 296 static const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { 297 .dram_dqm0 = 0x00000028, 298 .dram_dqm1 = 0x00000028, 299 .dram_dqm2 = 0x00000028, 300 .dram_dqm3 = 0x00000028, 301 .dram_ras = 0x00000020, 302 .dram_cas = 0x00000020, 303 .dram_odt0 = 0x00000020, 304 .dram_odt1 = 0x00000020, 305 .dram_sdba2 = 0x00000000, 306 .dram_sdcke0 = 0x00003000, 307 .dram_sdcke1 = 0x00003000, 308 .dram_sdclk_0 = 0x00000030, 309 .dram_sdqs0 = 0x00000028, 310 .dram_sdqs1 = 0x00000028, 311 .dram_sdqs2 = 0x00000028, 312 .dram_sdqs3 = 0x00000028, 313 .dram_reset = 0x00000020, 314 }; 315 316 static const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { 317 .grp_addds = 0x00000020, 318 .grp_ddrmode_ctl = 0x00020000, 319 .grp_ddrpke = 0x00000000, 320 .grp_ddrmode = 0x00020000, 321 .grp_b0ds = 0x00000028, 322 .grp_b1ds = 0x00000028, 323 .grp_ctlds = 0x00000020, 324 .grp_ddr_type = 0x000c0000, 325 .grp_b2ds = 0x00000028, 326 .grp_b3ds = 0x00000028, 327 }; 328 329 static const struct mx6_mmdc_calibration neo_mmcd_calib = { 330 .p0_mpwldectrl0 = 0x000E000B, 331 .p0_mpwldectrl1 = 0x000E0010, 332 .p0_mpdgctrl0 = 0x41600158, 333 .p0_mpdgctrl1 = 0x01500140, 334 .p0_mprddlctl = 0x3A383E3E, 335 .p0_mpwrdlctl = 0x3A383C38, 336 }; 337 338 static const struct mx6_mmdc_calibration neo_basic_mmcd_calib = { 339 .p0_mpwldectrl0 = 0x001E0022, 340 .p0_mpwldectrl1 = 0x001C0019, 341 .p0_mpdgctrl0 = 0x41540150, 342 .p0_mpdgctrl1 = 0x01440138, 343 .p0_mprddlctl = 0x403E4644, 344 .p0_mpwrdlctl = 0x3C3A4038, 345 }; 346 347 /* MT41K256M16 */ 348 static struct mx6_ddr3_cfg neo_mem_ddr = { 349 .mem_speed = 1600, 350 .density = 4, 351 .width = 16, 352 .banks = 8, 353 .rowaddr = 15, 354 .coladdr = 10, 355 .pagesz = 2, 356 .trcd = 1375, 357 .trcmin = 4875, 358 .trasmin = 3500, 359 }; 360 361 /* MT41K128M16 */ 362 static struct mx6_ddr3_cfg neo_basic_mem_ddr = { 363 .mem_speed = 1600, 364 .density = 2, 365 .width = 16, 366 .banks = 8, 367 .rowaddr = 14, 368 .coladdr = 10, 369 .pagesz = 2, 370 .trcd = 1375, 371 .trcmin = 4875, 372 .trasmin = 3500, 373 }; 374 375 static void ccgr_init(void) 376 { 377 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 378 379 writel(0xFFFFFFFF, &ccm->CCGR0); 380 writel(0xFFFFFFFF, &ccm->CCGR1); 381 writel(0xFFFFFFFF, &ccm->CCGR2); 382 writel(0xFFFFFFFF, &ccm->CCGR3); 383 writel(0xFFFFFFFF, &ccm->CCGR4); 384 writel(0xFFFFFFFF, &ccm->CCGR5); 385 writel(0xFFFFFFFF, &ccm->CCGR6); 386 writel(0xFFFFFFFF, &ccm->CCGR7); 387 } 388 389 static void spl_dram_init(void) 390 { 391 int board = get_board_value(); 392 393 struct mx6_ddr_sysinfo sysinfo = { 394 .dsize = 1, /* width of data bus: 1 = 32 bits */ 395 .cs_density = 24, 396 .ncs = 1, 397 .cs1_mirror = 0, 398 .rtt_wr = 2, 399 .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ 400 .walat = 1, /* Write additional latency */ 401 .ralat = 5, /* Read additional latency */ 402 .mif3_mode = 3, /* Command prediction working mode */ 403 .bi_on = 1, /* Bank interleaving enabled */ 404 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ 405 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ 406 }; 407 408 mx6sx_dram_iocfg(32, &mx6_ddr_ioregs, &mx6_grp_ioregs); 409 if (board == UDOO_NEO_TYPE_BASIC || board == UDOO_NEO_TYPE_BASIC_KS) 410 mx6_dram_cfg(&sysinfo, &neo_basic_mmcd_calib, 411 &neo_basic_mem_ddr); 412 else 413 mx6_dram_cfg(&sysinfo, &neo_mmcd_calib, &neo_mem_ddr); 414 } 415 416 void board_init_f(ulong dummy) 417 { 418 ccgr_init(); 419 420 /* setup AIPS and disable watchdog */ 421 arch_cpu_init(); 422 423 board_early_init_f(); 424 425 /* setup GP timer */ 426 timer_init(); 427 428 /* UART clocks enabled and gd valid - init serial console */ 429 preloader_console_init(); 430 431 /* DDR initialization */ 432 spl_dram_init(); 433 434 /* Clear the BSS. */ 435 memset(__bss_start, 0, __bss_end - __bss_start); 436 437 /* load/boot image from boot device */ 438 board_init_r(NULL, 0); 439 } 440 441 #endif 442