1/* 2 * Copyright (C) 2014 - 2015 Markus Niebel <Markus.Niebel@tq-group.com> 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 * 6 * Refer doc/README.imximage for more details about how-to configure 7 * and create imximage boot image 8 * 9 * The syntax is taken as close as possible with the kwbimage 10 */ 11 12/* image version */ 13IMAGE_VERSION 2 14 15#define __ASSEMBLY__ 16#include <config.h> 17 18/* 19 * Boot Device : one of 20 * spi, sd (the board has no nand neither onenand) 21 */ 22#if defined(CONFIG_TQMA6X_MMC_BOOT) 23BOOT_FROM sd 24#elif defined(CONFIG_TQMA6X_SPI_BOOT) 25BOOT_FROM spi 26#endif 27 28#include "asm/arch/mx6-ddr.h" 29#include "asm/arch/iomux.h" 30#include "asm/arch/crm_regs.h" 31 32/* TQMa6DL DDR config Rev. 0100E */ 33/* IOMUX configuration */ 34DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 35DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 36DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00008030 37DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00008030 38DATA 4, MX6_IOM_DRAM_CAS, 0x00008030 39DATA 4, MX6_IOM_DRAM_RAS, 0x00008030 40DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 41DATA 4, MX6_IOM_DRAM_RESET, 0x000C3030 42DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 43DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00000000 44DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 45DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 46DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 47DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 48DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 49DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 50DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 51DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 52DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 53DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 54DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 55DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 56DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 57DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 58DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 59DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 60DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 61DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 62DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 63DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 64DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 65DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 66DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 67DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 68DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 69DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 70DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 71DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 72DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 73DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 74 75/* memory interface calibration values */ 76DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003 77DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003 78DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x00440048 79DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x003D003F 80DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x0029002D 81DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x002B0043 82DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x424C0250 83DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02300234 84DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4234023C 85DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x0224022C 86DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x48484C4C 87DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4C4E4E4C 88DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x36382C36 89DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x34343630 90DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 91DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 92DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 93DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 94DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 95DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 96DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 97DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 98DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 99DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 100 101/* configure memory interface */ 102DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002D 103DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 104DATA 4, MX6_MMDC_P0_MDCFG0, 0x3F435333 105DATA 4, MX6_MMDC_P0_MDCFG1, 0xB68E8B63 106DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB 107DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740 108DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 109DATA 4, MX6_MMDC_P0_MDRWD, 0x000026D2 110DATA 4, MX6_MMDC_P0_MDOR, 0x00431023 111DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 112DATA 4, MX6_MMDC_P0_MDCTL, 0x831A0000 113DATA 4, MX6_MMDC_P0_MDSCR, 0x00408032 114DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 115DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031 116DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030 117DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 118DATA 4, MX6_MMDC_P0_MDREF, 0x00007800 119DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00022222 120DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00022222 121DATA 4, MX6_MMDC_P0_MDPDC, 0x0002552D 122DATA 4, MX6_MMDC_P0_MAPSR, 0x00001006 123DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 124 125#include "clocks.cfg" 126