1 /* 2 * Copyright (C) 2012 Freescale Semiconductor, Inc. 3 * Author: Fabio Estevam <fabio.estevam@freescale.com> 4 * 5 * Copyright (C) 2013, 2014 TQ Systems (ported SabreSD to TQMa6x) 6 * Author: Markus Niebel <markus.niebel@tq-group.com> 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11 #include <asm/io.h> 12 #include <asm/arch/clock.h> 13 #include <asm/arch/mx6-pins.h> 14 #include <asm/arch/imx-regs.h> 15 #include <asm/arch/iomux.h> 16 #include <asm/arch/sys_proto.h> 17 #include <linux/errno.h> 18 #include <asm/gpio.h> 19 #include <asm/mach-imx/mxc_i2c.h> 20 21 #include <common.h> 22 #include <fsl_esdhc.h> 23 #include <linux/libfdt.h> 24 #include <malloc.h> 25 #include <i2c.h> 26 #include <micrel.h> 27 #include <miiphy.h> 28 #include <mmc.h> 29 #include <netdev.h> 30 31 #include "tqma6_bb.h" 32 33 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 34 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 35 36 #define USDHC_CLK_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 37 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ 40 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 41 42 #define GPIO_OUT_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 44 45 #define GPIO_IN_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ 46 PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 47 48 #define SPI_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 49 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS) 50 51 #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 52 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ 53 PAD_CTL_ODE | PAD_CTL_SRE_FAST) 54 55 #if defined(CONFIG_TQMA6Q) 56 57 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0790 58 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e07ac 59 60 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) 61 62 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII 0x02e0768 63 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM 0x02e0788 64 65 #else 66 67 #error "need to select module" 68 69 #endif 70 71 #define ENET_RX_PAD_CTRL (PAD_CTL_DSE_34ohm) 72 #define ENET_TX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_34ohm) 73 #define ENET_CLK_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 74 PAD_CTL_DSE_34ohm) 75 #define ENET_MDIO_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 76 PAD_CTL_DSE_60ohm) 77 78 /* disable on die termination for RGMII */ 79 #define IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE 0x00000000 80 /* optimised drive strength for 1.0 .. 1.3 V signal on RGMII */ 81 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P2V 0x00080000 82 /* optimised drive strength for 1.3 .. 2.5 V signal on RGMII */ 83 #define IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V 0x000C0000 84 85 #define ENET_PHY_RESET_GPIO IMX_GPIO_NR(1, 25) 86 87 static iomux_v3_cfg_t const mba6_enet_pads[] = { 88 NEW_PAD_CTRL(MX6_PAD_ENET_MDIO__ENET_MDIO, ENET_MDIO_PAD_CTRL), 89 NEW_PAD_CTRL(MX6_PAD_ENET_MDC__ENET_MDC, ENET_MDIO_PAD_CTRL), 90 91 NEW_PAD_CTRL(MX6_PAD_RGMII_TXC__RGMII_TXC, ENET_TX_PAD_CTRL), 92 NEW_PAD_CTRL(MX6_PAD_RGMII_TD0__RGMII_TD0, ENET_TX_PAD_CTRL), 93 NEW_PAD_CTRL(MX6_PAD_RGMII_TD1__RGMII_TD1, ENET_TX_PAD_CTRL), 94 NEW_PAD_CTRL(MX6_PAD_RGMII_TD2__RGMII_TD2, ENET_TX_PAD_CTRL), 95 NEW_PAD_CTRL(MX6_PAD_RGMII_TD3__RGMII_TD3, ENET_TX_PAD_CTRL), 96 NEW_PAD_CTRL(MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL, 97 ENET_TX_PAD_CTRL), 98 NEW_PAD_CTRL(MX6_PAD_ENET_REF_CLK__ENET_TX_CLK, ENET_CLK_PAD_CTRL), 99 /* 100 * these pins are also used for config strapping by phy 101 */ 102 NEW_PAD_CTRL(MX6_PAD_RGMII_RD0__RGMII_RD0, ENET_RX_PAD_CTRL), 103 NEW_PAD_CTRL(MX6_PAD_RGMII_RD1__RGMII_RD1, ENET_RX_PAD_CTRL), 104 NEW_PAD_CTRL(MX6_PAD_RGMII_RD2__RGMII_RD2, ENET_RX_PAD_CTRL), 105 NEW_PAD_CTRL(MX6_PAD_RGMII_RD3__RGMII_RD3, ENET_RX_PAD_CTRL), 106 NEW_PAD_CTRL(MX6_PAD_RGMII_RXC__RGMII_RXC, ENET_RX_PAD_CTRL), 107 NEW_PAD_CTRL(MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL, 108 ENET_RX_PAD_CTRL), 109 /* KSZ9031 PHY Reset */ 110 NEW_PAD_CTRL(MX6_PAD_ENET_CRS_DV__GPIO1_IO25, GPIO_OUT_PAD_CTRL), 111 }; 112 113 static void mba6_setup_iomuxc_enet(void) 114 { 115 struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 116 117 /* clear gpr1[ENET_CLK_SEL] for externel clock */ 118 clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); 119 120 __raw_writel(IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM_DISABLE, 121 (void *)IOMUX_SW_PAD_CTRL_GRP_RGMII_TERM); 122 __raw_writel(IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII_1P5V, 123 (void *)IOMUX_SW_PAD_CTRL_GRP_DDR_TYPE_RGMII); 124 125 imx_iomux_v3_setup_multiple_pads(mba6_enet_pads, 126 ARRAY_SIZE(mba6_enet_pads)); 127 128 /* Reset PHY */ 129 gpio_direction_output(ENET_PHY_RESET_GPIO , 0); 130 /* Need delay 10ms after power on according to KSZ9031 spec */ 131 mdelay(10); 132 gpio_set_value(ENET_PHY_RESET_GPIO, 1); 133 /* 134 * KSZ9031 manual: 100 usec wait time after reset before communication 135 * over MDIO 136 * BUGBUG: hardware has an RC const that needs > 10 msec from 0->1 on 137 * reset before the phy sees a high level 138 */ 139 mdelay(15); 140 } 141 142 static iomux_v3_cfg_t const mba6_uart2_pads[] = { 143 NEW_PAD_CTRL(MX6_PAD_SD4_DAT4__UART2_RX_DATA, UART_PAD_CTRL), 144 NEW_PAD_CTRL(MX6_PAD_SD4_DAT7__UART2_TX_DATA, UART_PAD_CTRL), 145 }; 146 147 static void mba6_setup_iomuxc_uart(void) 148 { 149 imx_iomux_v3_setup_multiple_pads(mba6_uart2_pads, 150 ARRAY_SIZE(mba6_uart2_pads)); 151 } 152 153 #define USDHC2_CD_GPIO IMX_GPIO_NR(1, 4) 154 #define USDHC2_WP_GPIO IMX_GPIO_NR(1, 2) 155 156 int tqma6_bb_board_mmc_getcd(struct mmc *mmc) 157 { 158 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 159 int ret = 0; 160 161 if (cfg->esdhc_base == USDHC2_BASE_ADDR) 162 ret = !gpio_get_value(USDHC2_CD_GPIO); 163 164 return ret; 165 } 166 167 int tqma6_bb_board_mmc_getwp(struct mmc *mmc) 168 { 169 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 170 int ret = 0; 171 172 if (cfg->esdhc_base == USDHC2_BASE_ADDR) 173 ret = gpio_get_value(USDHC2_WP_GPIO); 174 175 return ret; 176 } 177 178 static struct fsl_esdhc_cfg mba6_usdhc_cfg = { 179 .esdhc_base = USDHC2_BASE_ADDR, 180 .max_bus_width = 4, 181 }; 182 183 static iomux_v3_cfg_t const mba6_usdhc2_pads[] = { 184 NEW_PAD_CTRL(MX6_PAD_SD2_CLK__SD2_CLK, USDHC_CLK_PAD_CTRL), 185 NEW_PAD_CTRL(MX6_PAD_SD2_CMD__SD2_CMD, USDHC_PAD_CTRL), 186 NEW_PAD_CTRL(MX6_PAD_SD2_DAT0__SD2_DATA0, USDHC_PAD_CTRL), 187 NEW_PAD_CTRL(MX6_PAD_SD2_DAT1__SD2_DATA1, USDHC_PAD_CTRL), 188 NEW_PAD_CTRL(MX6_PAD_SD2_DAT2__SD2_DATA2, USDHC_PAD_CTRL), 189 NEW_PAD_CTRL(MX6_PAD_SD2_DAT3__SD2_DATA3, USDHC_PAD_CTRL), 190 /* CD */ 191 NEW_PAD_CTRL(MX6_PAD_GPIO_4__GPIO1_IO04, GPIO_IN_PAD_CTRL), 192 /* WP */ 193 NEW_PAD_CTRL(MX6_PAD_GPIO_2__GPIO1_IO02, GPIO_IN_PAD_CTRL), 194 }; 195 196 int tqma6_bb_board_mmc_init(bd_t *bis) 197 { 198 imx_iomux_v3_setup_multiple_pads(mba6_usdhc2_pads, 199 ARRAY_SIZE(mba6_usdhc2_pads)); 200 gpio_direction_input(USDHC2_CD_GPIO); 201 gpio_direction_input(USDHC2_WP_GPIO); 202 203 mba6_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); 204 if (fsl_esdhc_initialize(bis, &mba6_usdhc_cfg)) 205 puts("Warning: failed to initialize SD\n"); 206 207 return 0; 208 } 209 210 static struct i2c_pads_info mba6_i2c1_pads = { 211 /* I2C1: MBa6x */ 212 .scl = { 213 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__I2C1_SCL, 214 I2C_PAD_CTRL), 215 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT9__GPIO5_IO27, 216 I2C_PAD_CTRL), 217 .gp = IMX_GPIO_NR(5, 27) 218 }, 219 .sda = { 220 .i2c_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__I2C1_SDA, 221 I2C_PAD_CTRL), 222 .gpio_mode = NEW_PAD_CTRL(MX6_PAD_CSI0_DAT8__GPIO5_IO26, 223 I2C_PAD_CTRL), 224 .gp = IMX_GPIO_NR(5, 26) 225 } 226 }; 227 228 static void mba6_setup_i2c(void) 229 { 230 int ret; 231 /* 232 * use logical index for bus, e.g. I2C1 -> 0 233 * warn on error 234 */ 235 ret = setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &mba6_i2c1_pads); 236 if (ret) 237 printf("setup I2C1 failed: %d\n", ret); 238 } 239 240 int board_phy_config(struct phy_device *phydev) 241 { 242 /* 243 * optimized pad skew values depends on CPU variant on the TQMa6x module: 244 * CONFIG_TQMA6Q: i.MX6Q/D 245 * CONFIG_TQMA6S: i.MX6S 246 * CONFIG_TQMA6DL: i.MX6DL 247 */ 248 #if defined(CONFIG_TQMA6Q) 249 #define MBA6X_KSZ9031_CTRL_SKEW 0x0032 250 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff 251 #define MBA6X_KSZ9031_RX_SKEW 0x3333 252 #define MBA6X_KSZ9031_TX_SKEW 0x2036 253 #elif defined(CONFIG_TQMA6S) || defined(CONFIG_TQMA6DL) 254 #define MBA6X_KSZ9031_CTRL_SKEW 0x0030 255 #define MBA6X_KSZ9031_CLK_SKEW 0x03ff 256 #define MBA6X_KSZ9031_RX_SKEW 0x3333 257 #define MBA6X_KSZ9031_TX_SKEW 0x2052 258 #else 259 #error 260 #endif 261 /* min rx/tx ctrl delay */ 262 ksz9031_phy_extended_write(phydev, 2, 263 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 264 MII_KSZ9031_MOD_DATA_NO_POST_INC, 265 MBA6X_KSZ9031_CTRL_SKEW); 266 /* min rx delay */ 267 ksz9031_phy_extended_write(phydev, 2, 268 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 269 MII_KSZ9031_MOD_DATA_NO_POST_INC, 270 MBA6X_KSZ9031_RX_SKEW); 271 /* max tx delay */ 272 ksz9031_phy_extended_write(phydev, 2, 273 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 274 MII_KSZ9031_MOD_DATA_NO_POST_INC, 275 MBA6X_KSZ9031_TX_SKEW); 276 /* rx/tx clk skew */ 277 ksz9031_phy_extended_write(phydev, 2, 278 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 279 MII_KSZ9031_MOD_DATA_NO_POST_INC, 280 MBA6X_KSZ9031_CLK_SKEW); 281 282 phydev->drv->config(phydev); 283 284 return 0; 285 } 286 287 int board_eth_init(bd_t *bis) 288 { 289 uint32_t base = IMX_FEC_BASE; 290 struct mii_dev *bus = NULL; 291 struct phy_device *phydev = NULL; 292 int ret; 293 294 bus = fec_get_miibus(base, -1); 295 if (!bus) 296 return -EINVAL; 297 /* scan phy */ 298 phydev = phy_find_by_mask(bus, (0xf << CONFIG_FEC_MXC_PHYADDR), 299 PHY_INTERFACE_MODE_RGMII); 300 301 if (!phydev) { 302 ret = -EINVAL; 303 goto free_bus; 304 } 305 ret = fec_probe(bis, -1, base, bus, phydev); 306 if (ret) 307 goto free_phydev; 308 309 return 0; 310 311 free_phydev: 312 free(phydev); 313 free_bus: 314 free(bus); 315 return ret; 316 } 317 318 int tqma6_bb_board_early_init_f(void) 319 { 320 mba6_setup_iomuxc_uart(); 321 322 return 0; 323 } 324 325 int tqma6_bb_board_init(void) 326 { 327 mba6_setup_i2c(); 328 /* do it here - to have reset completed */ 329 mba6_setup_iomuxc_enet(); 330 331 return 0; 332 } 333 334 int tqma6_bb_board_late_init(void) 335 { 336 return 0; 337 } 338 339 const char *tqma6_bb_get_boardname(void) 340 { 341 return "MBa6x"; 342 } 343 344 /* 345 * Device Tree Support 346 */ 347 #if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) 348 void tqma6_bb_ft_board_setup(void *blob, bd_t *bd) 349 { 350 /* TBD */ 351 } 352 #endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ 353