1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2005 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 */ 6 7 #include <common.h> 8 #include <ioports.h> 9 #include <mpc83xx.h> 10 #include <asm/mpc8349_pci.h> 11 #include <i2c.h> 12 #include <miiphy.h> 13 #include <asm/mmu.h> 14 #include <pci.h> 15 #include <flash.h> 16 #include <mtd/cfi_flash.h> 17 18 DECLARE_GLOBAL_DATA_PTR; 19 20 #define IOSYNC asm("eieio") 21 #define ISYNC asm("isync") 22 #define SYNC asm("sync") 23 #define FPW FLASH_PORT_WIDTH 24 #define FPWV FLASH_PORT_WIDTHV 25 26 #define DDR_MAX_SIZE_PER_CS 0x20000000 27 28 #if defined(DDR_CASLAT_20) 29 #define TIMING_CASLAT TIMING_CFG1_CASLAT_20 30 #define MODE_CASLAT DDR_MODE_CASLAT_20 31 #else 32 #define TIMING_CASLAT TIMING_CFG1_CASLAT_25 33 #define MODE_CASLAT DDR_MODE_CASLAT_25 34 #endif 35 36 #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \ 37 CSCONFIG_COL_BIT_9) 38 39 /* External definitions */ 40 ulong flash_get_size (ulong base, int banknum); 41 42 /* Local functions */ 43 static int detect_num_flash_banks(void); 44 static long int get_ddr_bank_size(short cs, long *base); 45 static void set_cs_bounds(short cs, ulong base, ulong size); 46 static void set_cs_config(short cs, long config); 47 static void set_ddr_config(void); 48 49 /* Local variable */ 50 static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR; 51 52 /************************************************************************** 53 * Board initialzation after relocation to RAM. Used to detect the number 54 * of Flash banks on TQM834x. 55 */ 56 int board_early_init_r (void) { 57 /* sanity check, IMMARBAR should be mirrored at offset zero of IMMR */ 58 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) 59 return 0; 60 61 /* detect the number of Flash banks */ 62 return detect_num_flash_banks(); 63 } 64 65 /************************************************************************** 66 * DRAM initalization and size detection 67 */ 68 int dram_init(void) 69 { 70 long bank_size; 71 long size; 72 int cs; 73 74 /* during size detection, set up the max DDRLAW size */ 75 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; 76 im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); 77 78 /* set CS bounds to maximum size */ 79 for(cs = 0; cs < 4; ++cs) { 80 set_cs_bounds(cs, 81 CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS), 82 DDR_MAX_SIZE_PER_CS); 83 84 set_cs_config(cs, INITIAL_CS_CONFIG); 85 } 86 87 /* configure ddr controller */ 88 set_ddr_config(); 89 90 udelay(200); 91 92 /* enable DDR controller */ 93 im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | 94 SDRAM_CFG_SREN | 95 SDRAM_CFG_SDRAM_TYPE_DDR1); 96 SYNC; 97 98 /* size detection */ 99 debug("\n"); 100 size = 0; 101 for(cs = 0; cs < 4; ++cs) { 102 debug("\nDetecting Bank%d\n", cs); 103 104 bank_size = get_ddr_bank_size(cs, 105 (long *)(CONFIG_SYS_DDR_BASE + size)); 106 size += bank_size; 107 108 debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); 109 110 /* exit if less than one bank */ 111 if(size < DDR_MAX_SIZE_PER_CS) break; 112 } 113 114 gd->ram_size = size; 115 116 return 0; 117 } 118 119 /************************************************************************** 120 * checkboard() 121 */ 122 int checkboard (void) 123 { 124 puts("Board: TQM834x\n"); 125 126 #ifdef CONFIG_PCI 127 volatile immap_t * immr; 128 u32 w, f; 129 130 immr = (immap_t *)CONFIG_SYS_IMMR; 131 if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) { 132 printf("PCI: NOT in host mode..?!\n"); 133 return 0; 134 } 135 136 /* get bus width */ 137 w = 32; 138 if (immr->reset.rcwh & HRCWH_64_BIT_PCI) 139 w = 64; 140 141 /* get clock */ 142 f = gd->pci_clk; 143 144 printf("PCI1: %d bit, %d MHz\n", w, f / 1000000); 145 #else 146 printf("PCI: disabled\n"); 147 #endif 148 return 0; 149 } 150 151 152 /************************************************************************** 153 * 154 * Local functions 155 * 156 *************************************************************************/ 157 158 /************************************************************************** 159 * Detect the number of flash banks (1 or 2). Store it in 160 * a global variable tqm834x_num_flash_banks. 161 * Bank detection code based on the Monitor code. 162 */ 163 static int detect_num_flash_banks(void) 164 { 165 typedef unsigned long FLASH_PORT_WIDTH; 166 typedef volatile unsigned long FLASH_PORT_WIDTHV; 167 FPWV *bank1_base; 168 FPWV *bank2_base; 169 FPW bank1_read; 170 FPW bank2_read; 171 ulong bank1_size; 172 ulong bank2_size; 173 ulong total_size; 174 175 cfi_flash_num_flash_banks = 2; /* assume two banks */ 176 177 /* Get bank 1 and 2 information */ 178 bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0); 179 debug("Bank1 size: %lu\n", bank1_size); 180 bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1); 181 debug("Bank2 size: %lu\n", bank2_size); 182 total_size = bank1_size + bank2_size; 183 184 if (bank2_size > 0) { 185 /* Seems like we've got bank 2, but maybe it's mirrored 1 */ 186 187 /* Set the base addresses */ 188 bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE); 189 bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size); 190 191 /* Put bank 2 into CFI command mode and read */ 192 bank2_base[0x55] = 0x00980098; 193 IOSYNC; 194 ISYNC; 195 bank2_read = bank2_base[0x10]; 196 197 /* Read from bank 1 (it's in read mode) */ 198 bank1_read = bank1_base[0x10]; 199 200 /* Reset Flash */ 201 bank1_base[0] = 0x00F000F0; 202 bank2_base[0] = 0x00F000F0; 203 204 if (bank2_read == bank1_read) { 205 /* 206 * Looks like just one bank, but not sure yet. Let's 207 * read from bank 2 in autosoelect mode. 208 */ 209 bank2_base[0x0555] = 0x00AA00AA; 210 bank2_base[0x02AA] = 0x00550055; 211 bank2_base[0x0555] = 0x00900090; 212 IOSYNC; 213 ISYNC; 214 bank2_read = bank2_base[0x10]; 215 216 /* Read from bank 1 (it's in read mode) */ 217 bank1_read = bank1_base[0x10]; 218 219 /* Reset Flash */ 220 bank1_base[0] = 0x00F000F0; 221 bank2_base[0] = 0x00F000F0; 222 223 if (bank2_read == bank1_read) { 224 /* 225 * In both CFI command and autoselect modes, 226 * we got the some data reading from Flash. 227 * There is only one mirrored bank. 228 */ 229 cfi_flash_num_flash_banks = 1; 230 total_size = bank1_size; 231 } 232 } 233 } 234 235 debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks); 236 237 /* set OR0 and BR0 */ 238 set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | 239 (-(total_size) & OR_GPCM_AM)); 240 set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) | 241 (BR_MS_GPCM | BR_PS_32 | BR_V)); 242 243 return (0); 244 } 245 246 /************************************************************************* 247 * Detect the size of a ddr bank. Sets CS bounds and CS config accordingly. 248 */ 249 static long int get_ddr_bank_size(short cs, long *base) 250 { 251 /* This array lists all valid DDR SDRAM configurations, with 252 * Bank sizes in bytes. (Refer to Table 9-27 in the MPC8349E RM). 253 * The last entry has to to have size equal 0 and is igonred during 254 * autodection. Bank sizes must be in increasing order of size 255 */ 256 struct { 257 long row; 258 long col; 259 long size; 260 } conf[] = { 261 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_8, 32 << 20}, 262 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_9, 64 << 20}, 263 {CSCONFIG_ROW_BIT_12, CSCONFIG_COL_BIT_10, 128 << 20}, 264 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_9, 128 << 20}, 265 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_10, 256 << 20}, 266 {CSCONFIG_ROW_BIT_13, CSCONFIG_COL_BIT_11, 512 << 20}, 267 {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_10, 512 << 20}, 268 {CSCONFIG_ROW_BIT_14, CSCONFIG_COL_BIT_11, 1024 << 20}, 269 {0, 0, 0} 270 }; 271 272 int i; 273 int detected; 274 long size; 275 276 detected = -1; 277 for(i = 0; conf[i].size != 0; ++i) { 278 279 /* set sdram bank configuration */ 280 set_cs_config(cs, CSCONFIG_EN | conf[i].col | conf[i].row); 281 282 debug("Getting RAM size...\n"); 283 size = get_ram_size(base, DDR_MAX_SIZE_PER_CS); 284 285 if((size == conf[i].size) && (i == detected + 1)) 286 detected = i; 287 288 debug("Trying %ld x %ld (%ld MiB) at addr %p, detected: %ld MiB\n", 289 conf[i].row, 290 conf[i].col, 291 conf[i].size >> 20, 292 base, 293 size >> 20); 294 } 295 296 if(detected == -1){ 297 /* disable empty cs */ 298 debug("\nNo valid configurations for CS%d, disabling...\n", cs); 299 set_cs_config(cs, 0); 300 return 0; 301 } 302 303 debug("\nDetected configuration %ld x %ld (%ld MiB) at addr %p\n", 304 conf[detected].row, conf[detected].col, conf[detected].size >> 20, base); 305 306 /* configure cs ro detected params */ 307 set_cs_config(cs, CSCONFIG_EN | conf[detected].row | 308 conf[detected].col); 309 310 set_cs_bounds(cs, (long)base, conf[detected].size); 311 312 return(conf[detected].size); 313 } 314 315 /************************************************************************** 316 * Sets DDR bank CS bounds. 317 */ 318 static void set_cs_bounds(short cs, ulong base, ulong size) 319 { 320 debug("Setting bounds %08lx, %08lx for cs %d\n", base, size, cs); 321 if(size == 0){ 322 im->ddr.csbnds[cs].csbnds = 0x00000000; 323 } else { 324 im->ddr.csbnds[cs].csbnds = 325 ((base >> CSBNDS_SA_SHIFT) & CSBNDS_SA) | 326 (((base + size - 1) >> CSBNDS_EA_SHIFT) & 327 CSBNDS_EA); 328 } 329 SYNC; 330 } 331 332 /************************************************************************** 333 * Sets DDR banks CS configuration. 334 * config == 0x00000000 disables the CS. 335 */ 336 static void set_cs_config(short cs, long config) 337 { 338 debug("Setting config %08lx for cs %d\n", config, cs); 339 im->ddr.cs_config[cs] = config; 340 SYNC; 341 } 342 343 /************************************************************************** 344 * Sets DDR clocks, timings and configuration. 345 */ 346 static void set_ddr_config(void) { 347 /* clock control */ 348 im->ddr.sdram_clk_cntl = DDR_SDRAM_CLK_CNTL_SS_EN | 349 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05; 350 SYNC; 351 352 /* timing configuration */ 353 im->ddr.timing_cfg_1 = 354 (4 << TIMING_CFG1_PRETOACT_SHIFT) | 355 (7 << TIMING_CFG1_ACTTOPRE_SHIFT) | 356 (4 << TIMING_CFG1_ACTTORW_SHIFT) | 357 (5 << TIMING_CFG1_REFREC_SHIFT) | 358 (3 << TIMING_CFG1_WRREC_SHIFT) | 359 (3 << TIMING_CFG1_ACTTOACT_SHIFT) | 360 (1 << TIMING_CFG1_WRTORD_SHIFT) | 361 (TIMING_CFG1_CASLAT & TIMING_CASLAT); 362 363 im->ddr.timing_cfg_2 = 364 TIMING_CFG2_CPO_DEF | 365 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT); 366 SYNC; 367 368 /* don't enable DDR controller yet */ 369 im->ddr.sdram_cfg = 370 SDRAM_CFG_SREN | 371 SDRAM_CFG_SDRAM_TYPE_DDR1; 372 SYNC; 373 374 /* Set SDRAM mode */ 375 im->ddr.sdram_mode = 376 ((DDR_MODE_EXT_MODEREG | DDR_MODE_WEAK) << 377 SDRAM_MODE_ESD_SHIFT) | 378 ((DDR_MODE_MODEREG | DDR_MODE_BLEN_4) << 379 SDRAM_MODE_SD_SHIFT) | 380 ((DDR_MODE_CASLAT << SDRAM_MODE_SD_SHIFT) & 381 MODE_CASLAT); 382 SYNC; 383 384 /* Set fast SDRAM refresh rate */ 385 im->ddr.sdram_interval = 386 (DDR_REFINT_166MHZ_7US << SDRAM_INTERVAL_REFINT_SHIFT) | 387 (DDR_BSTOPRE << SDRAM_INTERVAL_BSTOPRE_SHIFT); 388 SYNC; 389 390 /* Workaround for DDR6 Erratum 391 * see MPC8349E Device Errata Rev.8, 2/2006 392 * This workaround influences the MPC internal "input enables" 393 * dependent on CAS latency and MPC revision. According to errata 394 * sheet the internal reserved registers for this workaround are 395 * not available from revision 2.0 and up. 396 */ 397 398 /* Get REVID from register SPRIDR. Skip workaround if rev >= 2.0 399 * (0x200) 400 */ 401 if ((im->sysconf.spridr & SPRIDR_REVID) < 0x200) { 402 403 /* There is a internal reserved register at IMMRBAR+0x2F00 404 * which has to be written with a certain value defined by 405 * errata sheet. 406 */ 407 u32 *reserved_p = (u32 *)((u8 *)im + 0x2f00); 408 409 #if defined(DDR_CASLAT_20) 410 *reserved_p = 0x201c0000; 411 #else 412 *reserved_p = 0x202c0000; 413 #endif 414 } 415 } 416 417 #ifdef CONFIG_OF_BOARD_SETUP 418 int ft_board_setup(void *blob, bd_t *bd) 419 { 420 ft_cpu_setup(blob, bd); 421 422 #ifdef CONFIG_PCI 423 ft_pci_setup(blob, bd); 424 #endif /* CONFIG_PCI */ 425 426 return 0; 427 } 428 #endif /* CONFIG_OF_BOARD_SETUP */ 429