1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 * 23 */ 24 25 #include <asm/mmu.h> 26 #include <common.h> 27 #include <pci.h> 28 29 #ifdef CONFIG_PCI 30 31 /* System RAM mapped to PCI space */ 32 #define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE 33 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE 34 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) 35 36 #ifndef CONFIG_PCI_PNP 37 static struct pci_config_table pci_tqm834x_config_table[] = { 38 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 39 PCI_IDSEL_NUMBER, PCI_ANY_ID, 40 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, 41 PCI_ENET0_MEMADDR, 42 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER 43 } 44 }, 45 {} 46 }; 47 #endif 48 49 static struct pci_controller pci1_hose = { 50 #ifndef CONFIG_PCI_PNP 51 config_table:pci_tqm834x_config_table, 52 #endif 53 }; 54 55 56 /************************************************************************** 57 * pci_init_board() 58 * 59 * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since 60 * per TQM834x design physical connections to external devices (PCI sockets) 61 * are routed only to the PCI1 we do not account for the second one - this code 62 * supports PCI1 module only. Should support for the PCI2 be required in the 63 * future it needs a separate pci_controller structure (above) and handling - 64 * please refer to other boards' implementation for dual PCI host controllers, 65 * for example board/Marvell/db64360/pci.c, pci_init_board() 66 * 67 */ 68 void 69 pci_init_board(void) 70 { 71 volatile immap_t * immr; 72 volatile clk83xx_t * clk; 73 volatile law83xx_t * pci_law; 74 volatile pot83xx_t * pci_pot; 75 volatile pcictrl83xx_t * pci_ctrl; 76 volatile pciconf83xx_t * pci_conf; 77 u16 reg16; 78 u32 reg32; 79 struct pci_controller * hose; 80 81 immr = (immap_t *)CONFIG_SYS_IMMR; 82 clk = (clk83xx_t *)&immr->clk; 83 pci_law = immr->sysconf.pcilaw; 84 pci_pot = immr->ios.pot; 85 pci_ctrl = immr->pci_ctrl; 86 pci_conf = immr->pci_conf; 87 88 hose = &pci1_hose; 89 90 /* 91 * Configure PCI controller and PCI_CLK_OUTPUT 92 */ 93 94 /* 95 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one 96 * line actually used for clocking all external PCI devices in TQM83xx. 97 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for 98 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 99 * are known to hang the board; this issue is under investigation 100 * (13 oct 05) 101 */ 102 reg32 = OCCR_PCICOE1; 103 #if 0 104 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ 105 reg32 = 0xff000000; 106 #endif 107 if (clk->spmr & SPMR_CKID) { 108 /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR 109 * fields accordingly */ 110 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); 111 112 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ 113 | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ 114 | OCCR_PCICD6 | OCCR_PCICD7); 115 } 116 117 clk->occr = reg32; 118 udelay(2000); 119 120 /* 121 * Release PCI RST Output signal 122 */ 123 pci_ctrl[0].gcr = 0; 124 udelay(2000); 125 pci_ctrl[0].gcr = 1; 126 udelay(2000); 127 128 /* 129 * Configure PCI Local Access Windows 130 */ 131 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 132 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; 133 134 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 135 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; 136 137 /* 138 * Configure PCI Outbound Translation Windows 139 */ 140 141 /* PCI1 mem space */ 142 pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK; 143 pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK; 144 pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK); 145 146 /* PCI1 IO space */ 147 pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK; 148 pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK; 149 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK); 150 151 /* 152 * Configure PCI Inbound Translation Windows 153 */ 154 155 /* we need RAM mapped to PCI space for the devices to 156 * access main memory */ 157 pci_ctrl[0].pitar1 = 0x0; 158 pci_ctrl[0].pibar1 = 0x0; 159 pci_ctrl[0].piebar1 = 0x0; 160 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP | PIWAR_IWS_256M; 161 162 hose->first_busno = 0; 163 hose->last_busno = 0xff; 164 165 /* PCI memory space */ 166 pci_set_region(hose->regions + 0, 167 CONFIG_SYS_PCI1_MEM_BASE, 168 CONFIG_SYS_PCI1_MEM_PHYS, 169 CONFIG_SYS_PCI1_MEM_SIZE, 170 PCI_REGION_MEM); 171 172 /* PCI IO space */ 173 pci_set_region(hose->regions + 1, 174 CONFIG_SYS_PCI1_IO_BASE, 175 CONFIG_SYS_PCI1_IO_PHYS, 176 CONFIG_SYS_PCI1_IO_SIZE, 177 PCI_REGION_IO); 178 179 /* System memory space */ 180 pci_set_region(hose->regions + 2, 181 CONFIG_PCI_SYS_MEM_BUS, 182 CONFIG_PCI_SYS_MEM_PHYS, 183 CONFIG_PCI_SYS_MEM_SIZE, 184 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY); 185 186 hose->region_count = 3; 187 188 pci_setup_indirect(hose, 189 (CONFIG_SYS_IMMR+0x8300), 190 (CONFIG_SYS_IMMR+0x8304)); 191 192 pci_register_hose(hose); 193 194 /* 195 * Write to Command register 196 */ 197 reg16 = 0xff; 198 pci_hose_read_config_word (hose, PCI_BDF(0,0,0), PCI_COMMAND, 199 ®16); 200 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 201 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_COMMAND, 202 reg16); 203 204 /* 205 * Clear non-reserved bits in status register. 206 */ 207 pci_hose_write_config_word(hose, PCI_BDF(0,0,0), PCI_STATUS, 208 0xffff); 209 pci_hose_write_config_byte(hose, PCI_BDF(0,0,0), PCI_LATENCY_TIMER, 210 0x80); 211 212 #ifdef CONFIG_PCI_SCAN_SHOW 213 printf("PCI: Bus Dev VenId DevId Class Int\n"); 214 #endif 215 /* 216 * Hose scan. 217 */ 218 hose->last_busno = pci_hose_scan(hose); 219 } 220 #endif /* CONFIG_PCI */ 221