1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <asm/mmu.h> 10 #include <asm/io.h> 11 #include <common.h> 12 #include <mpc83xx.h> 13 #include <pci.h> 14 #include <i2c.h> 15 #include <asm/fsl_i2c.h> 16 17 DECLARE_GLOBAL_DATA_PTR; 18 19 static struct pci_region pci1_regions[] = { 20 { 21 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 22 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 23 size: CONFIG_SYS_PCI1_MEM_SIZE, 24 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 25 }, 26 { 27 bus_start: CONFIG_SYS_PCI1_IO_BASE, 28 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 29 size: CONFIG_SYS_PCI1_IO_SIZE, 30 flags: PCI_REGION_IO 31 }, 32 { 33 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 34 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 35 size: CONFIG_SYS_PCI1_MMIO_SIZE, 36 flags: PCI_REGION_MEM 37 }, 38 }; 39 40 /* 41 * pci_init_board() 42 * 43 * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since 44 * per TQM834x design physical connections to external devices (PCI sockets) 45 * are routed only to the PCI1 we do not account for the second one - this code 46 * supports PCI1 module only. Should support for the PCI2 be required in the 47 * future it needs a separate pci_controller structure (above) and handling - 48 * please refer to other boards' implementation for dual PCI host controllers, 49 * for example board/Marvell/db64360/pci.c, pci_init_board() 50 * 51 */ 52 void 53 pci_init_board(void) 54 { 55 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 56 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 57 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 58 struct pci_region *reg[] = { pci1_regions }; 59 u32 reg32; 60 61 /* 62 * Configure PCI controller and PCI_CLK_OUTPUT 63 * 64 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one 65 * line actually used for clocking all external PCI devices in TQM83xx. 66 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for 67 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 68 * are known to hang the board; this issue is under investigation 69 * (13 oct 05) 70 */ 71 reg32 = OCCR_PCICOE1; 72 #if 0 73 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ 74 reg32 = 0xff000000; 75 #endif 76 if (clk->spmr & SPMR_CKID) { 77 /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR 78 * fields accordingly */ 79 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); 80 81 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ 82 | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ 83 | OCCR_PCICD6 | OCCR_PCICD7); 84 } 85 86 clk->occr = reg32; 87 udelay(2000); 88 89 /* Configure PCI Local Access Windows */ 90 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 91 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; 92 93 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 94 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; 95 96 udelay(2000); 97 98 mpc83xx_pci_init(1, reg); 99 } 100