1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2005 4 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 5 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 6 */ 7 8 #include <asm/mmu.h> 9 #include <asm/io.h> 10 #include <common.h> 11 #include <mpc83xx.h> 12 #include <pci.h> 13 #include <i2c.h> 14 #include <asm/fsl_i2c.h> 15 16 static struct pci_region pci1_regions[] = { 17 { 18 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 19 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 20 size: CONFIG_SYS_PCI1_MEM_SIZE, 21 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 22 }, 23 { 24 bus_start: CONFIG_SYS_PCI1_IO_BASE, 25 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 26 size: CONFIG_SYS_PCI1_IO_SIZE, 27 flags: PCI_REGION_IO 28 }, 29 { 30 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 31 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 32 size: CONFIG_SYS_PCI1_MMIO_SIZE, 33 flags: PCI_REGION_MEM 34 }, 35 }; 36 37 /* 38 * pci_init_board() 39 * 40 * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since 41 * per TQM834x design physical connections to external devices (PCI sockets) 42 * are routed only to the PCI1 we do not account for the second one - this code 43 * supports PCI1 module only. Should support for the PCI2 be required in the 44 * future it needs a separate pci_controller structure (above) and handling - 45 * please refer to other boards' implementation for dual PCI host controllers, 46 * for example board/Marvell/db64360/pci.c, pci_init_board() 47 * 48 */ 49 void 50 pci_init_board(void) 51 { 52 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 53 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 54 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 55 struct pci_region *reg[] = { pci1_regions }; 56 u32 reg32; 57 58 /* 59 * Configure PCI controller and PCI_CLK_OUTPUT 60 * 61 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one 62 * line actually used for clocking all external PCI devices in TQM83xx. 63 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for 64 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 65 * are known to hang the board; this issue is under investigation 66 * (13 oct 05) 67 */ 68 reg32 = OCCR_PCICOE1; 69 #if 0 70 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ 71 reg32 = 0xff000000; 72 #endif 73 if (clk->spmr & SPMR_CKID) { 74 /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR 75 * fields accordingly */ 76 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); 77 78 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ 79 | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ 80 | OCCR_PCICD6 | OCCR_PCICD7); 81 } 82 83 clk->occr = reg32; 84 udelay(2000); 85 86 /* Configure PCI Local Access Windows */ 87 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 88 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; 89 90 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 91 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; 92 93 udelay(2000); 94 95 mpc83xx_pci_init(1, reg); 96 } 97