1 /* 2 * (C) Copyright 2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc. 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 * 24 */ 25 26 #include <asm/mmu.h> 27 #include <asm/io.h> 28 #include <common.h> 29 #include <mpc83xx.h> 30 #include <pci.h> 31 #include <i2c.h> 32 #include <asm/fsl_i2c.h> 33 34 DECLARE_GLOBAL_DATA_PTR; 35 36 static struct pci_region pci1_regions[] = { 37 { 38 bus_start: CONFIG_SYS_PCI1_MEM_BASE, 39 phys_start: CONFIG_SYS_PCI1_MEM_PHYS, 40 size: CONFIG_SYS_PCI1_MEM_SIZE, 41 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH 42 }, 43 { 44 bus_start: CONFIG_SYS_PCI1_IO_BASE, 45 phys_start: CONFIG_SYS_PCI1_IO_PHYS, 46 size: CONFIG_SYS_PCI1_IO_SIZE, 47 flags: PCI_REGION_IO 48 }, 49 { 50 bus_start: CONFIG_SYS_PCI1_MMIO_BASE, 51 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS, 52 size: CONFIG_SYS_PCI1_MMIO_SIZE, 53 flags: PCI_REGION_MEM 54 }, 55 }; 56 57 /* 58 * pci_init_board() 59 * 60 * NOTICE: MPC8349 internally has two PCI controllers (PCI1 and PCI2) but since 61 * per TQM834x design physical connections to external devices (PCI sockets) 62 * are routed only to the PCI1 we do not account for the second one - this code 63 * supports PCI1 module only. Should support for the PCI2 be required in the 64 * future it needs a separate pci_controller structure (above) and handling - 65 * please refer to other boards' implementation for dual PCI host controllers, 66 * for example board/Marvell/db64360/pci.c, pci_init_board() 67 * 68 */ 69 void 70 pci_init_board(void) 71 { 72 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; 73 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; 74 volatile law83xx_t *pci_law = immr->sysconf.pcilaw; 75 struct pci_region *reg[] = { pci1_regions }; 76 u32 reg32; 77 78 /* 79 * Configure PCI controller and PCI_CLK_OUTPUT 80 * 81 * WARNING! only PCI_CLK_OUTPUT1 is enabled here as this is the one 82 * line actually used for clocking all external PCI devices in TQM83xx. 83 * Enabling other PCI_CLK_OUTPUT lines may lead to board's hang for 84 * unknown reasons - particularly PCI_CLK_OUTPUT6 and PCI_CLK_OUTPUT7 85 * are known to hang the board; this issue is under investigation 86 * (13 oct 05) 87 */ 88 reg32 = OCCR_PCICOE1; 89 #if 0 90 /* enabling all PCI_CLK_OUTPUT lines HANGS the board... */ 91 reg32 = 0xff000000; 92 #endif 93 if (clk->spmr & SPMR_CKID) { 94 /* PCI Clock is half CONFIG_83XX_CLKIN so need to set up OCCR 95 * fields accordingly */ 96 reg32 |= (OCCR_PCI1CR | OCCR_PCI2CR); 97 98 reg32 |= (OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 \ 99 | OCCR_PCICD3 | OCCR_PCICD4 | OCCR_PCICD5 \ 100 | OCCR_PCICD6 | OCCR_PCICD7); 101 } 102 103 clk->occr = reg32; 104 udelay(2000); 105 106 /* Configure PCI Local Access Windows */ 107 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR; 108 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M; 109 110 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; 111 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M; 112 113 udelay(2000); 114 115 mpc83xx_pci_init(1, reg, 0); 116 } 117