1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Toradex, Inc. 4 * 5 * Based on vf610twr.c: 6 * Copyright 2013 Freescale Semiconductor, Inc. 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux-vf610.h> 13 #include <asm/arch/ddrmc-vf610.h> 14 #include <asm/arch/crm_regs.h> 15 #include <asm/arch/clock.h> 16 #include <mmc.h> 17 #include <fdt_support.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_dcu_fb.h> 20 #include <jffs2/load_kernel.h> 21 #include <miiphy.h> 22 #include <mtd_node.h> 23 #include <netdev.h> 24 #include <i2c.h> 25 #include <g_dnl.h> 26 #include <asm/gpio.h> 27 #include <usb.h> 28 #include "../common/tdx-common.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) 34 35 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 36 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 37 38 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 39 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 40 41 #define USB_PEN_GPIO 83 42 #define USB_CDET_GPIO 102 43 44 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { 45 /* levelling */ 46 { DDRMC_CR97_WRLVL_EN, 97 }, 47 { DDRMC_CR98_WRLVL_DL_0(0), 98 }, 48 { DDRMC_CR99_WRLVL_DL_1(0), 99 }, 49 { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, 50 { DDRMC_CR105_RDLVL_DL_0(0), 105 }, 51 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, 52 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, 53 /* AXI */ 54 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, 55 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, 56 { DDRMC_CR120_AXI0_PRI1_RPRI(2) | 57 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, 58 { DDRMC_CR121_AXI0_PRI3_RPRI(2) | 59 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, 60 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 61 DDRMC_CR122_AXI0_PRIRLX(100), 122 }, 62 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | 63 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, 64 { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, 65 { DDRMC_CR126_PHY_RDLAT(8), 126 }, 66 { DDRMC_CR132_WRLAT_ADJ(5) | 67 DDRMC_CR132_RDLAT_ADJ(6), 132 }, 68 { DDRMC_CR137_PHYCTL_DL(2), 137 }, 69 { DDRMC_CR138_PHY_WRLV_MXDL(256) | 70 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, 71 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 72 DDRMC_CR139_PHY_WRLV_DLL(3) | 73 DDRMC_CR139_PHY_WRLV_EN(3), 139 }, 74 { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, 75 { DDRMC_CR143_RDLV_GAT_MXDL(1536) | 76 DDRMC_CR143_RDLV_MXDL(128), 143 }, 77 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | 78 DDRMC_CR144_PHY_RDLV_DLL(3) | 79 DDRMC_CR144_PHY_RDLV_EN(3), 144 }, 80 { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, 81 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, 82 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, 83 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, 84 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | 85 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, 86 87 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 88 DDRMC_CR154_PAD_ZQ_MODE(1) | 89 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 90 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, 91 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, 92 { DDRMC_CR158_TWR(6), 158 }, 93 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | 94 DDRMC_CR161_TODTH_WR(2), 161 }, 95 /* end marker */ 96 { 0, -1 } 97 }; 98 99 static const iomux_v3_cfg_t usb_pads[] = { 100 VF610_PAD_PTD4__GPIO_83, 101 VF610_PAD_PTC29__GPIO_102, 102 }; 103 104 int dram_init(void) 105 { 106 static const struct ddr3_jedec_timings timings = { 107 .tinit = 5, 108 .trst_pwron = 80000, 109 .cke_inactive = 200000, 110 .wrlat = 5, 111 .caslat_lin = 12, 112 .trc = 21, 113 .trrd = 4, 114 .tccd = 4, 115 .tbst_int_interval = 0, 116 .tfaw = 20, 117 .trp = 6, 118 .twtr = 4, 119 .tras_min = 15, 120 .tmrd = 4, 121 .trtp = 4, 122 .tras_max = 28080, 123 .tmod = 12, 124 .tckesr = 4, 125 .tcke = 3, 126 .trcd_int = 6, 127 .tras_lockout = 0, 128 .tdal = 12, 129 .bstlen = 3, 130 .tdll = 512, 131 .trp_ab = 6, 132 .tref = 3120, 133 .trfc = 64, 134 .tref_int = 0, 135 .tpdex = 3, 136 .txpdll = 10, 137 .txsnr = 48, 138 .txsr = 468, 139 .cksrx = 5, 140 .cksre = 5, 141 .freq_chg_en = 0, 142 .zqcl = 256, 143 .zqinit = 512, 144 .zqcs = 64, 145 .ref_per_zq = 64, 146 .zqcs_rotate = 0, 147 .aprebit = 10, 148 .cmd_age_cnt = 64, 149 .age_cnt = 64, 150 .q_fullness = 7, 151 .odt_rd_mapcs0 = 0, 152 .odt_wr_mapcs0 = 1, 153 .wlmrd = 40, 154 .wldqsen = 25, 155 }; 156 157 ddrmc_setup_iomux(NULL, 0); 158 159 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2); 160 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 161 162 return 0; 163 } 164 165 static void setup_iomux_uart(void) 166 { 167 static const iomux_v3_cfg_t uart_pads[] = { 168 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), 169 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), 170 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL), 171 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL), 172 }; 173 174 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 175 } 176 177 static void setup_iomux_enet(void) 178 { 179 static const iomux_v3_cfg_t enet0_pads[] = { 180 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL), 181 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL), 182 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL), 183 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL), 184 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL), 185 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL), 186 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL), 187 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL), 188 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL), 189 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL), 190 }; 191 192 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 193 } 194 195 static void setup_iomux_i2c(void) 196 { 197 static const iomux_v3_cfg_t i2c0_pads[] = { 198 VF610_PAD_PTB14__I2C0_SCL, 199 VF610_PAD_PTB15__I2C0_SDA, 200 }; 201 202 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); 203 } 204 205 #ifdef CONFIG_NAND_VF610_NFC 206 static void setup_iomux_nfc(void) 207 { 208 static const iomux_v3_cfg_t nfc_pads[] = { 209 VF610_PAD_PTD23__NF_IO7, 210 VF610_PAD_PTD22__NF_IO6, 211 VF610_PAD_PTD21__NF_IO5, 212 VF610_PAD_PTD20__NF_IO4, 213 VF610_PAD_PTD19__NF_IO3, 214 VF610_PAD_PTD18__NF_IO2, 215 VF610_PAD_PTD17__NF_IO1, 216 VF610_PAD_PTD16__NF_IO0, 217 VF610_PAD_PTB24__NF_WE_B, 218 VF610_PAD_PTB25__NF_CE0_B, 219 VF610_PAD_PTB27__NF_RE_B, 220 VF610_PAD_PTC26__NF_RB_B, 221 VF610_PAD_PTC27__NF_ALE, 222 VF610_PAD_PTC28__NF_CLE 223 }; 224 225 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 226 } 227 #endif 228 229 #ifdef CONFIG_FSL_DSPI 230 static void setup_iomux_dspi(void) 231 { 232 static const iomux_v3_cfg_t dspi1_pads[] = { 233 VF610_PAD_PTD5__DSPI1_CS0, 234 VF610_PAD_PTD6__DSPI1_SIN, 235 VF610_PAD_PTD7__DSPI1_SOUT, 236 VF610_PAD_PTD8__DSPI1_SCK, 237 }; 238 239 imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); 240 } 241 #endif 242 243 #ifdef CONFIG_VYBRID_GPIO 244 static void setup_iomux_gpio(void) 245 { 246 static const iomux_v3_cfg_t gpio_pads[] = { 247 VF610_PAD_PTA17__GPIO_7, 248 VF610_PAD_PTA20__GPIO_10, 249 VF610_PAD_PTA21__GPIO_11, 250 VF610_PAD_PTA30__GPIO_20, 251 VF610_PAD_PTA31__GPIO_21, 252 VF610_PAD_PTB0__GPIO_22, 253 VF610_PAD_PTB1__GPIO_23, 254 VF610_PAD_PTB6__GPIO_28, 255 VF610_PAD_PTB7__GPIO_29, 256 VF610_PAD_PTB8__GPIO_30, 257 VF610_PAD_PTB9__GPIO_31, 258 VF610_PAD_PTB12__GPIO_34, 259 VF610_PAD_PTB13__GPIO_35, 260 VF610_PAD_PTB16__GPIO_38, 261 VF610_PAD_PTB17__GPIO_39, 262 VF610_PAD_PTB18__GPIO_40, 263 VF610_PAD_PTB21__GPIO_43, 264 VF610_PAD_PTB22__GPIO_44, 265 VF610_PAD_PTC0__GPIO_45, 266 VF610_PAD_PTC1__GPIO_46, 267 VF610_PAD_PTC2__GPIO_47, 268 VF610_PAD_PTC3__GPIO_48, 269 VF610_PAD_PTC4__GPIO_49, 270 VF610_PAD_PTC5__GPIO_50, 271 VF610_PAD_PTC6__GPIO_51, 272 VF610_PAD_PTC7__GPIO_52, 273 VF610_PAD_PTC8__GPIO_53, 274 VF610_PAD_PTD31__GPIO_63, 275 VF610_PAD_PTD30__GPIO_64, 276 VF610_PAD_PTD29__GPIO_65, 277 VF610_PAD_PTD28__GPIO_66, 278 VF610_PAD_PTD27__GPIO_67, 279 VF610_PAD_PTD26__GPIO_68, 280 VF610_PAD_PTD25__GPIO_69, 281 VF610_PAD_PTD24__GPIO_70, 282 VF610_PAD_PTD9__GPIO_88, 283 VF610_PAD_PTD10__GPIO_89, 284 VF610_PAD_PTD11__GPIO_90, 285 VF610_PAD_PTD12__GPIO_91, 286 VF610_PAD_PTD13__GPIO_92, 287 VF610_PAD_PTB23__GPIO_93, 288 VF610_PAD_PTB26__GPIO_96, 289 VF610_PAD_PTB28__GPIO_98, 290 VF610_PAD_PTC30__GPIO_103, 291 VF610_PAD_PTA7__GPIO_134, 292 }; 293 294 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); 295 } 296 #endif 297 298 #ifdef CONFIG_VIDEO_FSL_DCU_FB 299 static void setup_iomux_fsl_dcu(void) 300 { 301 static const iomux_v3_cfg_t dcu0_pads[] = { 302 VF610_PAD_PTE0__DCU0_HSYNC, 303 VF610_PAD_PTE1__DCU0_VSYNC, 304 VF610_PAD_PTE2__DCU0_PCLK, 305 VF610_PAD_PTE4__DCU0_DE, 306 VF610_PAD_PTE5__DCU0_R0, 307 VF610_PAD_PTE6__DCU0_R1, 308 VF610_PAD_PTE7__DCU0_R2, 309 VF610_PAD_PTE8__DCU0_R3, 310 VF610_PAD_PTE9__DCU0_R4, 311 VF610_PAD_PTE10__DCU0_R5, 312 VF610_PAD_PTE11__DCU0_R6, 313 VF610_PAD_PTE12__DCU0_R7, 314 VF610_PAD_PTE13__DCU0_G0, 315 VF610_PAD_PTE14__DCU0_G1, 316 VF610_PAD_PTE15__DCU0_G2, 317 VF610_PAD_PTE16__DCU0_G3, 318 VF610_PAD_PTE17__DCU0_G4, 319 VF610_PAD_PTE18__DCU0_G5, 320 VF610_PAD_PTE19__DCU0_G6, 321 VF610_PAD_PTE20__DCU0_G7, 322 VF610_PAD_PTE21__DCU0_B0, 323 VF610_PAD_PTE22__DCU0_B1, 324 VF610_PAD_PTE23__DCU0_B2, 325 VF610_PAD_PTE24__DCU0_B3, 326 VF610_PAD_PTE25__DCU0_B4, 327 VF610_PAD_PTE26__DCU0_B5, 328 VF610_PAD_PTE27__DCU0_B6, 329 VF610_PAD_PTE28__DCU0_B7, 330 }; 331 332 imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads)); 333 } 334 335 static void setup_tcon(void) 336 { 337 setbits_le32(TCON0_BASE_ADDR, (1 << 29)); 338 } 339 #endif 340 341 #ifdef CONFIG_FSL_ESDHC 342 struct fsl_esdhc_cfg esdhc_cfg[1] = { 343 {ESDHC1_BASE_ADDR}, 344 }; 345 346 int board_mmc_getcd(struct mmc *mmc) 347 { 348 /* eSDHC1 is always present */ 349 return 1; 350 } 351 352 int board_mmc_init(bd_t *bis) 353 { 354 static const iomux_v3_cfg_t esdhc1_pads[] = { 355 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 356 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 357 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 358 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 359 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 360 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 361 }; 362 363 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 364 365 imx_iomux_v3_setup_multiple_pads( 366 esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 367 368 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 369 } 370 #endif 371 372 static inline int is_colibri_vf61(void) 373 { 374 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; 375 376 /* 377 * Detect board type by Level 2 Cache: VF50 don't have any 378 * Level 2 Cache. 379 */ 380 return !!mscm->cpxcfg1; 381 } 382 383 static void clock_init(void) 384 { 385 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 386 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 387 u32 pfd_clk_sel, ddr_clk_sel; 388 389 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 390 CCM_CCGR0_UART0_CTRL_MASK); 391 #ifdef CONFIG_FSL_DSPI 392 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); 393 #endif 394 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 395 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 396 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 397 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 398 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 399 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); 400 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 401 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); 402 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 403 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 404 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); 405 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 406 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 407 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 408 CCM_CCGR7_SDHC1_CTRL_MASK); 409 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 410 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 411 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 412 CCM_CCGR10_NFC_CTRL_MASK); 413 414 #ifdef CONFIG_USB_EHCI_VF 415 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK); 416 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK); 417 418 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | 419 ANADIG_PLL3_CTRL_POWERDOWN | 420 ANADIG_PLL3_CTRL_DIV_SELECT, 421 ANADIG_PLL3_CTRL_ENABLE); 422 clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS | 423 ANADIG_PLL7_CTRL_POWERDOWN | 424 ANADIG_PLL7_CTRL_DIV_SELECT, 425 ANADIG_PLL7_CTRL_ENABLE); 426 #endif 427 428 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | 429 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | 430 ANADIG_PLL5_CTRL_DIV_SELECT); 431 432 if (is_colibri_vf61()) { 433 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | 434 ANADIG_PLL2_CTRL_POWERDOWN, 435 ANADIG_PLL2_CTRL_ENABLE | 436 ANADIG_PLL2_CTRL_DIV_SELECT); 437 } 438 439 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 440 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 441 442 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 443 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 444 445 /* See "Typical PLL Configuration" */ 446 if (is_colibri_vf61()) { 447 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1); 448 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); 449 } else { 450 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3); 451 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1); 452 } 453 454 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | 455 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | 456 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | 457 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | 458 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | 459 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) | 460 CCM_CCSR_SYS_CLK_SEL(4)); 461 462 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 463 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 464 CCM_CACRR_ARM_CLK_DIV(0)); 465 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 466 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | 467 CCM_CSCMR1_NFC_CLK_SEL(0)); 468 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 469 CCM_CSCDR1_RMII_CLK_EN); 470 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 471 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 472 CCM_CSCDR2_NFC_EN); 473 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 474 CCM_CSCDR3_NFC_PRE_DIV(3)); 475 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 476 CCM_CSCMR2_RMII_CLK_SEL(2)); 477 478 #ifdef CONFIG_VIDEO_FSL_DCU_FB 479 setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK); 480 setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK); 481 #endif 482 } 483 484 static void mscm_init(void) 485 { 486 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 487 int i; 488 489 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 490 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 491 } 492 493 int board_phy_config(struct phy_device *phydev) 494 { 495 if (phydev->drv->config) 496 phydev->drv->config(phydev); 497 498 return 0; 499 } 500 501 int board_early_init_f(void) 502 { 503 clock_init(); 504 mscm_init(); 505 506 setup_iomux_uart(); 507 setup_iomux_enet(); 508 setup_iomux_i2c(); 509 #ifdef CONFIG_NAND_VF610_NFC 510 setup_iomux_nfc(); 511 #endif 512 513 #ifdef CONFIG_VYBRID_GPIO 514 setup_iomux_gpio(); 515 #endif 516 517 #ifdef CONFIG_FSL_DSPI 518 setup_iomux_dspi(); 519 #endif 520 521 #ifdef CONFIG_VIDEO_FSL_DCU_FB 522 setup_tcon(); 523 setup_iomux_fsl_dcu(); 524 #endif 525 526 return 0; 527 } 528 529 #ifdef CONFIG_BOARD_LATE_INIT 530 int board_late_init(void) 531 { 532 struct src *src = (struct src *)SRC_BASE_ADDR; 533 534 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT) 535 == SRC_SBMR2_BMOD_SERIAL) { 536 printf("Serial Downloader recovery mode, disable autoboot\n"); 537 env_set("bootdelay", "-1"); 538 } 539 540 return 0; 541 } 542 #endif /* CONFIG_BOARD_LATE_INIT */ 543 544 int board_init(void) 545 { 546 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; 547 548 /* address of boot parameters */ 549 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 550 551 /* 552 * Enable external 32K Oscillator 553 * 554 * The internal clock experiences significant drift 555 * so we must use the external oscillator in order 556 * to maintain correct time in the hwclock 557 */ 558 559 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); 560 561 #ifdef CONFIG_USB_EHCI_VF 562 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); 563 #endif 564 565 return 0; 566 } 567 568 int checkboard(void) 569 { 570 if (is_colibri_vf61()) 571 puts("Board: Colibri VF61\n"); 572 else 573 puts("Board: Colibri VF50\n"); 574 575 return 0; 576 } 577 578 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 579 int ft_board_setup(void *blob, bd_t *bd) 580 { 581 int ret = 0; 582 #ifdef CONFIG_FDT_FIXUP_PARTITIONS 583 static struct node_info nodes[] = { 584 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 585 }; 586 587 /* Update partition nodes using info from mtdparts env var */ 588 puts(" Updating MTD partitions...\n"); 589 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 590 #endif 591 #ifdef CONFIG_VIDEO_FSL_DCU_FB 592 ret = fsl_dcu_fixedfb_setup(blob); 593 if (ret) 594 return ret; 595 #endif 596 597 return ft_common_board_setup(blob, bd); 598 } 599 #endif 600 601 #ifdef CONFIG_USB_EHCI_VF 602 int board_ehci_hcd_init(int port) 603 { 604 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 605 606 switch (port) { 607 case 0: 608 /* USBC does not have PEN, also configured as USB client only */ 609 break; 610 case 1: 611 gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); 612 gpio_direction_output(USB_PEN_GPIO, 0); 613 break; 614 } 615 return 0; 616 } 617 618 int board_usb_phy_mode(int port) 619 { 620 switch (port) { 621 case 0: 622 /* 623 * Port 0 is used only in client mode on Colibri Vybrid modules 624 * Check for state of USB client gpio pin and accordingly return 625 * USB_INIT_DEVICE or USB_INIT_HOST. 626 */ 627 if (gpio_get_value(USB_CDET_GPIO)) 628 return USB_INIT_DEVICE; 629 else 630 return USB_INIT_HOST; 631 case 1: 632 /* Port 1 is used only in host mode on Colibri Vybrid modules */ 633 return USB_INIT_HOST; 634 default: 635 /* 636 * There are only two USB controllers on Vybrid. Ideally we will 637 * not reach here. However return USB_INIT_HOST if we do. 638 */ 639 return USB_INIT_HOST; 640 } 641 } 642 #endif 643