1 /* 2 * Copyright 2015 Toradex, Inc. 3 * 4 * Based on vf610twr.c: 5 * Copyright 2013 Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux-vf610.h> 14 #include <asm/arch/ddrmc-vf610.h> 15 #include <asm/arch/crm_regs.h> 16 #include <asm/arch/clock.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 #include <i2c.h> 22 #include <g_dnl.h> 23 #include <asm/gpio.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 28 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) 29 30 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 31 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 32 33 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 34 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 35 36 #define USB_PEN_GPIO 83 37 38 static const iomux_v3_cfg_t usb_pads[] = { 39 VF610_PAD_PTD4__GPIO_83, 40 }; 41 42 int dram_init(void) 43 { 44 static const struct ddr3_jedec_timings timings = { 45 .tinit = 5, 46 .trst_pwron = 80000, 47 .cke_inactive = 200000, 48 .wrlat = 5, 49 .caslat_lin = 12, 50 .trc = 21, 51 .trrd = 4, 52 .tccd = 4, 53 .tfaw = 20, 54 .trp = 6, 55 .twtr = 4, 56 .tras_min = 15, 57 .tmrd = 4, 58 .trtp = 4, 59 .tras_max = 28080, 60 .tmod = 12, 61 .tckesr = 4, 62 .tcke = 3, 63 .trcd_int = 6, 64 .tdal = 12, 65 .tdll = 512, 66 .trp_ab = 6, 67 .tref = 3120, 68 .trfc = 64, 69 .tpdex = 3, 70 .txpdll = 10, 71 .txsnr = 48, 72 .txsr = 468, 73 .cksrx = 5, 74 .cksre = 5, 75 .zqcl = 256, 76 .zqinit = 512, 77 .zqcs = 64, 78 .ref_per_zq = 64, 79 .aprebit = 10, 80 .wlmrd = 40, 81 .wldqsen = 25, 82 }; 83 84 ddrmc_setup_iomux(); 85 86 ddrmc_ctrl_init_ddr3(&timings, NULL, 1, 2); 87 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 88 89 return 0; 90 } 91 92 static void setup_iomux_uart(void) 93 { 94 static const iomux_v3_cfg_t uart_pads[] = { 95 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), 96 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), 97 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL), 98 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL), 99 }; 100 101 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 102 } 103 104 static void setup_iomux_enet(void) 105 { 106 static const iomux_v3_cfg_t enet0_pads[] = { 107 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL), 108 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL), 109 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL), 110 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL), 111 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL), 112 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL), 113 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL), 114 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL), 115 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL), 116 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL), 117 }; 118 119 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 120 } 121 122 static void setup_iomux_i2c(void) 123 { 124 static const iomux_v3_cfg_t i2c0_pads[] = { 125 VF610_PAD_PTB14__I2C0_SCL, 126 VF610_PAD_PTB15__I2C0_SDA, 127 }; 128 129 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); 130 } 131 132 #ifdef CONFIG_NAND_VF610_NFC 133 static void setup_iomux_nfc(void) 134 { 135 static const iomux_v3_cfg_t nfc_pads[] = { 136 VF610_PAD_PTD23__NF_IO7, 137 VF610_PAD_PTD22__NF_IO6, 138 VF610_PAD_PTD21__NF_IO5, 139 VF610_PAD_PTD20__NF_IO4, 140 VF610_PAD_PTD19__NF_IO3, 141 VF610_PAD_PTD18__NF_IO2, 142 VF610_PAD_PTD17__NF_IO1, 143 VF610_PAD_PTD16__NF_IO0, 144 VF610_PAD_PTB24__NF_WE_B, 145 VF610_PAD_PTB25__NF_CE0_B, 146 VF610_PAD_PTB27__NF_RE_B, 147 VF610_PAD_PTC26__NF_RB_B, 148 VF610_PAD_PTC27__NF_ALE, 149 VF610_PAD_PTC28__NF_CLE 150 }; 151 152 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 153 } 154 #endif 155 156 #ifdef CONFIG_FSL_DSPI 157 static void setup_iomux_dspi(void) 158 { 159 static const iomux_v3_cfg_t dspi1_pads[] = { 160 VF610_PAD_PTD5__DSPI1_CS0, 161 VF610_PAD_PTD6__DSPI1_SIN, 162 VF610_PAD_PTD7__DSPI1_SOUT, 163 VF610_PAD_PTD8__DSPI1_SCK, 164 }; 165 166 imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); 167 } 168 #endif 169 170 #ifdef CONFIG_VYBRID_GPIO 171 static void setup_iomux_gpio(void) 172 { 173 static const iomux_v3_cfg_t gpio_pads[] = { 174 VF610_PAD_PTA17__GPIO_7, 175 VF610_PAD_PTA20__GPIO_10, 176 VF610_PAD_PTA21__GPIO_11, 177 VF610_PAD_PTA30__GPIO_20, 178 VF610_PAD_PTA31__GPIO_21, 179 VF610_PAD_PTB0__GPIO_22, 180 VF610_PAD_PTB1__GPIO_23, 181 VF610_PAD_PTB6__GPIO_28, 182 VF610_PAD_PTB7__GPIO_29, 183 VF610_PAD_PTB8__GPIO_30, 184 VF610_PAD_PTB9__GPIO_31, 185 VF610_PAD_PTB12__GPIO_34, 186 VF610_PAD_PTB13__GPIO_35, 187 VF610_PAD_PTB16__GPIO_38, 188 VF610_PAD_PTB17__GPIO_39, 189 VF610_PAD_PTB18__GPIO_40, 190 VF610_PAD_PTB21__GPIO_43, 191 VF610_PAD_PTB22__GPIO_44, 192 VF610_PAD_PTC0__GPIO_45, 193 VF610_PAD_PTC1__GPIO_46, 194 VF610_PAD_PTC2__GPIO_47, 195 VF610_PAD_PTC3__GPIO_48, 196 VF610_PAD_PTC4__GPIO_49, 197 VF610_PAD_PTC5__GPIO_50, 198 VF610_PAD_PTC6__GPIO_51, 199 VF610_PAD_PTC7__GPIO_52, 200 VF610_PAD_PTC8__GPIO_53, 201 VF610_PAD_PTD31__GPIO_63, 202 VF610_PAD_PTD30__GPIO_64, 203 VF610_PAD_PTD29__GPIO_65, 204 VF610_PAD_PTD28__GPIO_66, 205 VF610_PAD_PTD27__GPIO_67, 206 VF610_PAD_PTD26__GPIO_68, 207 VF610_PAD_PTD25__GPIO_69, 208 VF610_PAD_PTD24__GPIO_70, 209 VF610_PAD_PTD9__GPIO_88, 210 VF610_PAD_PTD10__GPIO_89, 211 VF610_PAD_PTD11__GPIO_90, 212 VF610_PAD_PTD12__GPIO_91, 213 VF610_PAD_PTD13__GPIO_92, 214 VF610_PAD_PTB23__GPIO_93, 215 VF610_PAD_PTB26__GPIO_96, 216 VF610_PAD_PTB28__GPIO_98, 217 VF610_PAD_PTC29__GPIO_102, 218 VF610_PAD_PTC30__GPIO_103, 219 VF610_PAD_PTA7__GPIO_134, 220 }; 221 222 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); 223 } 224 #endif 225 226 #ifdef CONFIG_FSL_ESDHC 227 struct fsl_esdhc_cfg esdhc_cfg[1] = { 228 {ESDHC1_BASE_ADDR}, 229 }; 230 231 int board_mmc_getcd(struct mmc *mmc) 232 { 233 /* eSDHC1 is always present */ 234 return 1; 235 } 236 237 int board_mmc_init(bd_t *bis) 238 { 239 static const iomux_v3_cfg_t esdhc1_pads[] = { 240 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 241 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 242 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 243 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 244 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 245 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 246 }; 247 248 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 249 250 imx_iomux_v3_setup_multiple_pads( 251 esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 252 253 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 254 } 255 #endif 256 257 static inline int is_colibri_vf61(void) 258 { 259 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; 260 261 /* 262 * Detect board type by Level 2 Cache: VF50 don't have any 263 * Level 2 Cache. 264 */ 265 return !!mscm->cpxcfg1; 266 } 267 268 static void clock_init(void) 269 { 270 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 271 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 272 u32 pfd_clk_sel, ddr_clk_sel; 273 274 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 275 CCM_CCGR0_UART0_CTRL_MASK); 276 #ifdef CONFIG_FSL_DSPI 277 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); 278 #endif 279 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 280 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 281 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 282 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 283 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 284 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); 285 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 286 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); 287 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 288 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 289 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); 290 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 291 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 292 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 293 CCM_CCGR7_SDHC1_CTRL_MASK); 294 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 295 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 296 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 297 CCM_CCGR10_NFC_CTRL_MASK); 298 299 #ifdef CONFIG_CI_UDC 300 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK); 301 #endif 302 303 #ifdef CONFIG_USB_EHCI 304 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK); 305 #endif 306 307 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | 308 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | 309 ANADIG_PLL5_CTRL_DIV_SELECT); 310 311 if (is_colibri_vf61()) { 312 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | 313 ANADIG_PLL2_CTRL_POWERDOWN, 314 ANADIG_PLL2_CTRL_ENABLE | 315 ANADIG_PLL2_CTRL_DIV_SELECT); 316 } 317 318 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 319 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 320 321 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 322 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 323 324 /* See "Typical PLL Configuration" */ 325 if (is_colibri_vf61()) { 326 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1); 327 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); 328 } else { 329 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3); 330 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1); 331 } 332 333 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | 334 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | 335 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | 336 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | 337 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | 338 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) | 339 CCM_CCSR_SYS_CLK_SEL(4)); 340 341 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 342 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 343 CCM_CACRR_ARM_CLK_DIV(0)); 344 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 345 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | 346 CCM_CSCMR1_NFC_CLK_SEL(0)); 347 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 348 CCM_CSCDR1_RMII_CLK_EN); 349 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 350 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 351 CCM_CSCDR2_NFC_EN); 352 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 353 CCM_CSCDR3_NFC_PRE_DIV(5)); 354 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 355 CCM_CSCMR2_RMII_CLK_SEL(2)); 356 } 357 358 static void mscm_init(void) 359 { 360 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 361 int i; 362 363 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 364 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 365 } 366 367 int board_phy_config(struct phy_device *phydev) 368 { 369 if (phydev->drv->config) 370 phydev->drv->config(phydev); 371 372 return 0; 373 } 374 375 int board_early_init_f(void) 376 { 377 clock_init(); 378 mscm_init(); 379 380 setup_iomux_uart(); 381 setup_iomux_enet(); 382 setup_iomux_i2c(); 383 #ifdef CONFIG_NAND_VF610_NFC 384 setup_iomux_nfc(); 385 #endif 386 387 #ifdef CONFIG_VYBRID_GPIO 388 setup_iomux_gpio(); 389 #endif 390 391 #ifdef CONFIG_FSL_DSPI 392 setup_iomux_dspi(); 393 #endif 394 395 return 0; 396 } 397 398 #ifdef CONFIG_BOARD_LATE_INIT 399 int board_late_init(void) 400 { 401 struct src *src = (struct src *)SRC_BASE_ADDR; 402 403 /* Default memory arguments */ 404 if (!getenv("memargs")) { 405 switch (gd->ram_size) { 406 case 0x08000000: 407 /* 128 MB */ 408 setenv("memargs", "mem=128M"); 409 break; 410 case 0x10000000: 411 /* 256 MB */ 412 setenv("memargs", "mem=256M"); 413 break; 414 default: 415 printf("Failed detecting RAM size.\n"); 416 } 417 } 418 419 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT) 420 == SRC_SBMR2_BMOD_SERIAL) { 421 printf("Serial Downloader recovery mode, disable autoboot\n"); 422 setenv("bootdelay", "-1"); 423 } 424 425 return 0; 426 } 427 #endif /* CONFIG_BOARD_LATE_INIT */ 428 429 int board_init(void) 430 { 431 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; 432 433 /* address of boot parameters */ 434 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 435 436 /* 437 * Enable external 32K Oscillator 438 * 439 * The internal clock experiences significant drift 440 * so we must use the external oscillator in order 441 * to maintain correct time in the hwclock 442 */ 443 444 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); 445 446 return 0; 447 } 448 449 int checkboard(void) 450 { 451 if (is_colibri_vf61()) 452 puts("Board: Colibri VF61\n"); 453 else 454 puts("Board: Colibri VF50\n"); 455 456 return 0; 457 } 458 459 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) 460 { 461 unsigned short usb_pid; 462 463 put_unaligned(CONFIG_TRDX_VID, &dev->idVendor); 464 465 if (is_colibri_vf61()) 466 usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT; 467 else 468 usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT; 469 470 put_unaligned(usb_pid, &dev->idProduct); 471 472 return 0; 473 } 474 475 #ifdef CONFIG_USB_EHCI_VF 476 int board_ehci_hcd_init(int port) 477 { 478 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 479 480 switch (port) { 481 case 0: 482 /* USBC does not have PEN, also configured as USB client only */ 483 break; 484 case 1: 485 gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); 486 gpio_direction_output(USB_PEN_GPIO, 0); 487 break; 488 } 489 return 0; 490 } 491 #endif 492