1 /* 2 * Copyright 2015 Toradex, Inc. 3 * 4 * Based on vf610twr.c: 5 * Copyright 2013 Freescale Semiconductor, Inc. 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/io.h> 12 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/iomux-vf610.h> 14 #include <asm/arch/ddrmc-vf610.h> 15 #include <asm/arch/crm_regs.h> 16 #include <asm/arch/clock.h> 17 #include <mmc.h> 18 #include <fsl_esdhc.h> 19 #include <miiphy.h> 20 #include <netdev.h> 21 #include <i2c.h> 22 #include <g_dnl.h> 23 #include <asm/gpio.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 28 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) 29 30 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 31 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 32 33 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 34 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 35 36 #define USB_PEN_GPIO 83 37 38 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { 39 /* levelling */ 40 { DDRMC_CR97_WRLVL_EN, 97 }, 41 { DDRMC_CR98_WRLVL_DL_0(0), 98 }, 42 { DDRMC_CR99_WRLVL_DL_1(0), 99 }, 43 { DDRMC_CR102_RDLVL_REG_EN | DDRMC_CR102_RDLVL_GT_REGEN, 102 }, 44 { DDRMC_CR105_RDLVL_DL_0(0), 105 }, 45 { DDRMC_CR106_RDLVL_GTDL_0(4), 106 }, 46 { DDRMC_CR110_RDLVL_DL_1(0) | DDRMC_CR110_RDLVL_GTDL_1(4), 110 }, 47 /* AXI */ 48 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, 49 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, 50 { DDRMC_CR120_AXI0_PRI1_RPRI(2) | 51 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, 52 { DDRMC_CR121_AXI0_PRI3_RPRI(2) | 53 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, 54 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 55 DDRMC_CR122_AXI0_PRIRLX(100), 122 }, 56 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | 57 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, 58 { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, 59 { DDRMC_CR126_PHY_RDLAT(8), 126 }, 60 { DDRMC_CR132_WRLAT_ADJ(5) | 61 DDRMC_CR132_RDLAT_ADJ(6), 132 }, 62 { DDRMC_CR137_PHYCTL_DL(2), 137 }, 63 { DDRMC_CR138_PHY_WRLV_MXDL(256) | 64 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, 65 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 66 DDRMC_CR139_PHY_WRLV_DLL(3) | 67 DDRMC_CR139_PHY_WRLV_EN(3), 139 }, 68 { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, 69 { DDRMC_CR143_RDLV_GAT_MXDL(1536) | 70 DDRMC_CR143_RDLV_MXDL(128), 143 }, 71 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | 72 DDRMC_CR144_PHY_RDLV_DLL(3) | 73 DDRMC_CR144_PHY_RDLV_EN(3), 144 }, 74 { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, 75 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, 76 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, 77 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, 78 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | 79 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, 80 81 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 82 DDRMC_CR154_PAD_ZQ_MODE(1) | 83 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 84 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, 85 { DDRMC_CR155_PAD_ODT_BYTE1(1) | DDRMC_CR155_PAD_ODT_BYTE0(1), 155 }, 86 { DDRMC_CR158_TWR(6), 158 }, 87 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | 88 DDRMC_CR161_TODTH_WR(2), 161 }, 89 /* end marker */ 90 { 0, -1 } 91 }; 92 93 static const iomux_v3_cfg_t usb_pads[] = { 94 VF610_PAD_PTD4__GPIO_83, 95 }; 96 97 int dram_init(void) 98 { 99 static const struct ddr3_jedec_timings timings = { 100 .tinit = 5, 101 .trst_pwron = 80000, 102 .cke_inactive = 200000, 103 .wrlat = 5, 104 .caslat_lin = 12, 105 .trc = 21, 106 .trrd = 4, 107 .tccd = 4, 108 .tbst_int_interval = 0, 109 .tfaw = 20, 110 .trp = 6, 111 .twtr = 4, 112 .tras_min = 15, 113 .tmrd = 4, 114 .trtp = 4, 115 .tras_max = 28080, 116 .tmod = 12, 117 .tckesr = 4, 118 .tcke = 3, 119 .trcd_int = 6, 120 .tras_lockout = 0, 121 .tdal = 12, 122 .bstlen = 3, 123 .tdll = 512, 124 .trp_ab = 6, 125 .tref = 3120, 126 .trfc = 64, 127 .tref_int = 0, 128 .tpdex = 3, 129 .txpdll = 10, 130 .txsnr = 48, 131 .txsr = 468, 132 .cksrx = 5, 133 .cksre = 5, 134 .freq_chg_en = 0, 135 .zqcl = 256, 136 .zqinit = 512, 137 .zqcs = 64, 138 .ref_per_zq = 64, 139 .zqcs_rotate = 0, 140 .aprebit = 10, 141 .cmd_age_cnt = 64, 142 .age_cnt = 64, 143 .q_fullness = 7, 144 .odt_rd_mapcs0 = 0, 145 .odt_wr_mapcs0 = 1, 146 .wlmrd = 40, 147 .wldqsen = 25, 148 }; 149 150 ddrmc_setup_iomux(NULL, 0); 151 152 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2); 153 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 154 155 return 0; 156 } 157 158 static void setup_iomux_uart(void) 159 { 160 static const iomux_v3_cfg_t uart_pads[] = { 161 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), 162 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), 163 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL), 164 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL), 165 }; 166 167 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 168 } 169 170 static void setup_iomux_enet(void) 171 { 172 static const iomux_v3_cfg_t enet0_pads[] = { 173 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL), 174 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL), 175 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL), 176 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL), 177 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL), 178 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL), 179 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL), 180 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL), 181 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL), 182 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL), 183 }; 184 185 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 186 } 187 188 static void setup_iomux_i2c(void) 189 { 190 static const iomux_v3_cfg_t i2c0_pads[] = { 191 VF610_PAD_PTB14__I2C0_SCL, 192 VF610_PAD_PTB15__I2C0_SDA, 193 }; 194 195 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); 196 } 197 198 #ifdef CONFIG_NAND_VF610_NFC 199 static void setup_iomux_nfc(void) 200 { 201 static const iomux_v3_cfg_t nfc_pads[] = { 202 VF610_PAD_PTD23__NF_IO7, 203 VF610_PAD_PTD22__NF_IO6, 204 VF610_PAD_PTD21__NF_IO5, 205 VF610_PAD_PTD20__NF_IO4, 206 VF610_PAD_PTD19__NF_IO3, 207 VF610_PAD_PTD18__NF_IO2, 208 VF610_PAD_PTD17__NF_IO1, 209 VF610_PAD_PTD16__NF_IO0, 210 VF610_PAD_PTB24__NF_WE_B, 211 VF610_PAD_PTB25__NF_CE0_B, 212 VF610_PAD_PTB27__NF_RE_B, 213 VF610_PAD_PTC26__NF_RB_B, 214 VF610_PAD_PTC27__NF_ALE, 215 VF610_PAD_PTC28__NF_CLE 216 }; 217 218 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 219 } 220 #endif 221 222 #ifdef CONFIG_FSL_DSPI 223 static void setup_iomux_dspi(void) 224 { 225 static const iomux_v3_cfg_t dspi1_pads[] = { 226 VF610_PAD_PTD5__DSPI1_CS0, 227 VF610_PAD_PTD6__DSPI1_SIN, 228 VF610_PAD_PTD7__DSPI1_SOUT, 229 VF610_PAD_PTD8__DSPI1_SCK, 230 }; 231 232 imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); 233 } 234 #endif 235 236 #ifdef CONFIG_VYBRID_GPIO 237 static void setup_iomux_gpio(void) 238 { 239 static const iomux_v3_cfg_t gpio_pads[] = { 240 VF610_PAD_PTA17__GPIO_7, 241 VF610_PAD_PTA20__GPIO_10, 242 VF610_PAD_PTA21__GPIO_11, 243 VF610_PAD_PTA30__GPIO_20, 244 VF610_PAD_PTA31__GPIO_21, 245 VF610_PAD_PTB0__GPIO_22, 246 VF610_PAD_PTB1__GPIO_23, 247 VF610_PAD_PTB6__GPIO_28, 248 VF610_PAD_PTB7__GPIO_29, 249 VF610_PAD_PTB8__GPIO_30, 250 VF610_PAD_PTB9__GPIO_31, 251 VF610_PAD_PTB12__GPIO_34, 252 VF610_PAD_PTB13__GPIO_35, 253 VF610_PAD_PTB16__GPIO_38, 254 VF610_PAD_PTB17__GPIO_39, 255 VF610_PAD_PTB18__GPIO_40, 256 VF610_PAD_PTB21__GPIO_43, 257 VF610_PAD_PTB22__GPIO_44, 258 VF610_PAD_PTC0__GPIO_45, 259 VF610_PAD_PTC1__GPIO_46, 260 VF610_PAD_PTC2__GPIO_47, 261 VF610_PAD_PTC3__GPIO_48, 262 VF610_PAD_PTC4__GPIO_49, 263 VF610_PAD_PTC5__GPIO_50, 264 VF610_PAD_PTC6__GPIO_51, 265 VF610_PAD_PTC7__GPIO_52, 266 VF610_PAD_PTC8__GPIO_53, 267 VF610_PAD_PTD31__GPIO_63, 268 VF610_PAD_PTD30__GPIO_64, 269 VF610_PAD_PTD29__GPIO_65, 270 VF610_PAD_PTD28__GPIO_66, 271 VF610_PAD_PTD27__GPIO_67, 272 VF610_PAD_PTD26__GPIO_68, 273 VF610_PAD_PTD25__GPIO_69, 274 VF610_PAD_PTD24__GPIO_70, 275 VF610_PAD_PTD9__GPIO_88, 276 VF610_PAD_PTD10__GPIO_89, 277 VF610_PAD_PTD11__GPIO_90, 278 VF610_PAD_PTD12__GPIO_91, 279 VF610_PAD_PTD13__GPIO_92, 280 VF610_PAD_PTB23__GPIO_93, 281 VF610_PAD_PTB26__GPIO_96, 282 VF610_PAD_PTB28__GPIO_98, 283 VF610_PAD_PTC29__GPIO_102, 284 VF610_PAD_PTC30__GPIO_103, 285 VF610_PAD_PTA7__GPIO_134, 286 }; 287 288 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); 289 } 290 #endif 291 292 #ifdef CONFIG_FSL_ESDHC 293 struct fsl_esdhc_cfg esdhc_cfg[1] = { 294 {ESDHC1_BASE_ADDR}, 295 }; 296 297 int board_mmc_getcd(struct mmc *mmc) 298 { 299 /* eSDHC1 is always present */ 300 return 1; 301 } 302 303 int board_mmc_init(bd_t *bis) 304 { 305 static const iomux_v3_cfg_t esdhc1_pads[] = { 306 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 307 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 308 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 309 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 310 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 311 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 312 }; 313 314 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 315 316 imx_iomux_v3_setup_multiple_pads( 317 esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 318 319 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 320 } 321 #endif 322 323 static inline int is_colibri_vf61(void) 324 { 325 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; 326 327 /* 328 * Detect board type by Level 2 Cache: VF50 don't have any 329 * Level 2 Cache. 330 */ 331 return !!mscm->cpxcfg1; 332 } 333 334 static void clock_init(void) 335 { 336 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 337 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 338 u32 pfd_clk_sel, ddr_clk_sel; 339 340 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 341 CCM_CCGR0_UART0_CTRL_MASK); 342 #ifdef CONFIG_FSL_DSPI 343 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); 344 #endif 345 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 346 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 347 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 348 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 349 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 350 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); 351 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 352 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); 353 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 354 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 355 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); 356 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 357 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 358 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 359 CCM_CCGR7_SDHC1_CTRL_MASK); 360 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 361 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 362 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 363 CCM_CCGR10_NFC_CTRL_MASK); 364 365 #ifdef CONFIG_CI_UDC 366 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK); 367 #endif 368 369 #ifdef CONFIG_USB_EHCI 370 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK); 371 #endif 372 373 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | 374 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | 375 ANADIG_PLL5_CTRL_DIV_SELECT); 376 377 if (is_colibri_vf61()) { 378 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | 379 ANADIG_PLL2_CTRL_POWERDOWN, 380 ANADIG_PLL2_CTRL_ENABLE | 381 ANADIG_PLL2_CTRL_DIV_SELECT); 382 } 383 384 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 385 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 386 387 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 388 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 389 390 /* See "Typical PLL Configuration" */ 391 if (is_colibri_vf61()) { 392 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1); 393 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); 394 } else { 395 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3); 396 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1); 397 } 398 399 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | 400 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | 401 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | 402 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | 403 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | 404 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) | 405 CCM_CCSR_SYS_CLK_SEL(4)); 406 407 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 408 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 409 CCM_CACRR_ARM_CLK_DIV(0)); 410 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 411 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | 412 CCM_CSCMR1_NFC_CLK_SEL(0)); 413 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 414 CCM_CSCDR1_RMII_CLK_EN); 415 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 416 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 417 CCM_CSCDR2_NFC_EN); 418 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 419 CCM_CSCDR3_NFC_PRE_DIV(5)); 420 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 421 CCM_CSCMR2_RMII_CLK_SEL(2)); 422 } 423 424 static void mscm_init(void) 425 { 426 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 427 int i; 428 429 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 430 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 431 } 432 433 int board_phy_config(struct phy_device *phydev) 434 { 435 if (phydev->drv->config) 436 phydev->drv->config(phydev); 437 438 return 0; 439 } 440 441 int board_early_init_f(void) 442 { 443 clock_init(); 444 mscm_init(); 445 446 setup_iomux_uart(); 447 setup_iomux_enet(); 448 setup_iomux_i2c(); 449 #ifdef CONFIG_NAND_VF610_NFC 450 setup_iomux_nfc(); 451 #endif 452 453 #ifdef CONFIG_VYBRID_GPIO 454 setup_iomux_gpio(); 455 #endif 456 457 #ifdef CONFIG_FSL_DSPI 458 setup_iomux_dspi(); 459 #endif 460 461 return 0; 462 } 463 464 #ifdef CONFIG_BOARD_LATE_INIT 465 int board_late_init(void) 466 { 467 struct src *src = (struct src *)SRC_BASE_ADDR; 468 469 /* Default memory arguments */ 470 if (!getenv("memargs")) { 471 switch (gd->ram_size) { 472 case 0x08000000: 473 /* 128 MB */ 474 setenv("memargs", "mem=128M"); 475 break; 476 case 0x10000000: 477 /* 256 MB */ 478 setenv("memargs", "mem=256M"); 479 break; 480 default: 481 printf("Failed detecting RAM size.\n"); 482 } 483 } 484 485 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT) 486 == SRC_SBMR2_BMOD_SERIAL) { 487 printf("Serial Downloader recovery mode, disable autoboot\n"); 488 setenv("bootdelay", "-1"); 489 } 490 491 return 0; 492 } 493 #endif /* CONFIG_BOARD_LATE_INIT */ 494 495 int board_init(void) 496 { 497 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; 498 499 /* address of boot parameters */ 500 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 501 502 /* 503 * Enable external 32K Oscillator 504 * 505 * The internal clock experiences significant drift 506 * so we must use the external oscillator in order 507 * to maintain correct time in the hwclock 508 */ 509 510 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); 511 512 return 0; 513 } 514 515 int checkboard(void) 516 { 517 if (is_colibri_vf61()) 518 puts("Board: Colibri VF61\n"); 519 else 520 puts("Board: Colibri VF50\n"); 521 522 return 0; 523 } 524 525 int g_dnl_bind_fixup(struct usb_device_descriptor *dev, const char *name) 526 { 527 unsigned short usb_pid; 528 529 put_unaligned(CONFIG_TRDX_VID, &dev->idVendor); 530 531 if (is_colibri_vf61()) 532 usb_pid = CONFIG_TRDX_PID_COLIBRI_VF61IT; 533 else 534 usb_pid = CONFIG_TRDX_PID_COLIBRI_VF50IT; 535 536 put_unaligned(usb_pid, &dev->idProduct); 537 538 return 0; 539 } 540 541 #ifdef CONFIG_USB_EHCI_VF 542 int board_ehci_hcd_init(int port) 543 { 544 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 545 546 switch (port) { 547 case 0: 548 /* USBC does not have PEN, also configured as USB client only */ 549 break; 550 case 1: 551 gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); 552 gpio_direction_output(USB_PEN_GPIO, 0); 553 break; 554 } 555 return 0; 556 } 557 #endif 558