1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2015 Toradex, Inc.
4  *
5  * Based on vf610twr.c:
6  * Copyright 2013 Freescale Semiconductor, Inc.
7  */
8 
9 #include <common.h>
10 #include <asm/io.h>
11 #include <asm/arch/imx-regs.h>
12 #include <asm/arch/iomux-vf610.h>
13 #include <asm/arch/ddrmc-vf610.h>
14 #include <asm/arch/crm_regs.h>
15 #include <asm/arch/clock.h>
16 #include <mmc.h>
17 #include <fdt_support.h>
18 #include <fsl_esdhc.h>
19 #include <fsl_dcu_fb.h>
20 #include <jffs2/load_kernel.h>
21 #include <miiphy.h>
22 #include <mtd_node.h>
23 #include <netdev.h>
24 #include <i2c.h>
25 #include <g_dnl.h>
26 #include <asm/gpio.h>
27 #include <usb.h>
28 #include "../common/tdx-common.h"
29 
30 DECLARE_GLOBAL_DATA_PTR;
31 
32 #define UART_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
33 			PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE)
34 
35 #define ESDHC_PAD_CTRL	(PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \
36 			PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE)
37 
38 #define ENET_PAD_CTRL	(PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \
39 			PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE)
40 
41 #define USB_PEN_GPIO		83
42 #define USB_CDET_GPIO		102
43 #define PTC0_GPIO_45		45
44 
45 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = {
46 	/* AXI */
47 	{ DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 },
48 	{ DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 },
49 	{ DDRMC_CR120_AXI0_PRI1_RPRI(2) |
50 		   DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 },
51 	{ DDRMC_CR121_AXI0_PRI3_RPRI(2) |
52 		   DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 },
53 	{ DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) |
54 		   DDRMC_CR122_AXI0_PRIRLX(100), 122 },
55 	{ DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) |
56 		   DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 },
57 	{ DDRMC_CR124_AXI1_PRIRLX(100), 124 },
58 	{ DDRMC_CR126_PHY_RDLAT(8), 126 },
59 	{ DDRMC_CR132_WRLAT_ADJ(5) |
60 		   DDRMC_CR132_RDLAT_ADJ(6), 132 },
61 	{ DDRMC_CR137_PHYCTL_DL(2), 137 },
62 	{ DDRMC_CR138_PHY_WRLV_MXDL(256) |
63 		   DDRMC_CR138_PHYDRAM_CK_EN(1), 138 },
64 	{ DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) |
65 		   DDRMC_CR139_PHY_WRLV_DLL(3) |
66 		   DDRMC_CR139_PHY_WRLV_EN(3), 139 },
67 	{ DDRMC_CR140_PHY_WRLV_WW(64), 140 },
68 	{ DDRMC_CR143_RDLV_GAT_MXDL(1536) |
69 		   DDRMC_CR143_RDLV_MXDL(128), 143 },
70 	{ DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) |
71 		   DDRMC_CR144_PHY_RDLV_DLL(3) |
72 		   DDRMC_CR144_PHY_RDLV_EN(3), 144 },
73 	{ DDRMC_CR145_PHY_RDLV_RR(64), 145 },
74 	{ DDRMC_CR146_PHY_RDLVL_RESP(64), 146 },
75 	{ DDRMC_CR147_RDLV_RESP_MASK(983040), 147 },
76 	{ DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 },
77 	{ DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) |
78 		   DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 },
79 
80 	{ DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) |
81 		   DDRMC_CR154_PAD_ZQ_MODE(1) |
82 		   DDRMC_CR154_DDR_SEL_PAD_CONTR(3) |
83 		   DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 },
84 	{ DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 },
85 	{ DDRMC_CR158_TWR(6), 158 },
86 	{ DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) |
87 		   DDRMC_CR161_TODTH_WR(2), 161 },
88 	/* end marker */
89 	{ 0, -1 }
90 };
91 
92 static const iomux_v3_cfg_t usb_pads[] = {
93 	VF610_PAD_PTD4__GPIO_83,
94 	VF610_PAD_PTC29__GPIO_102,
95 };
96 
97 int dram_init(void)
98 {
99 	static const struct ddr3_jedec_timings timings = {
100 		.tinit             = 5,
101 		.trst_pwron        = 80000,
102 		.cke_inactive      = 200000,
103 		.wrlat             = 5,
104 		.caslat_lin        = 12,
105 		.trc               = 21,
106 		.trrd              = 4,
107 		.tccd              = 4,
108 		.tbst_int_interval = 0,
109 		.tfaw              = 20,
110 		.trp               = 6,
111 		.twtr              = 4,
112 		.tras_min          = 15,
113 		.tmrd              = 4,
114 		.trtp              = 4,
115 		.tras_max          = 28080,
116 		.tmod              = 12,
117 		.tckesr            = 4,
118 		.tcke              = 3,
119 		.trcd_int          = 6,
120 		.tras_lockout      = 0,
121 		.tdal              = 12,
122 		.bstlen            = 3,
123 		.tdll              = 512,
124 		.trp_ab            = 6,
125 		.tref              = 3120,
126 		.trfc              = 64,
127 		.tref_int          = 0,
128 		.tpdex             = 3,
129 		.txpdll            = 10,
130 		.txsnr             = 48,
131 		.txsr              = 468,
132 		.cksrx             = 5,
133 		.cksre             = 5,
134 		.freq_chg_en       = 0,
135 		.zqcl              = 256,
136 		.zqinit            = 512,
137 		.zqcs              = 64,
138 		.ref_per_zq        = 64,
139 		.zqcs_rotate       = 0,
140 		.aprebit           = 10,
141 		.cmd_age_cnt       = 64,
142 		.age_cnt           = 64,
143 		.q_fullness        = 7,
144 		.odt_rd_mapcs0     = 0,
145 		.odt_wr_mapcs0     = 1,
146 		.wlmrd             = 40,
147 		.wldqsen           = 25,
148 	};
149 
150 	ddrmc_setup_iomux(NULL, 0);
151 
152 	ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2);
153 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
154 
155 	return 0;
156 }
157 
158 static void setup_iomux_uart(void)
159 {
160 	static const iomux_v3_cfg_t uart_pads[] = {
161 		NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL),
162 		NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL),
163 		NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL),
164 		NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL),
165 	};
166 
167 	imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
168 }
169 
170 static void setup_iomux_enet(void)
171 {
172 	static const iomux_v3_cfg_t enet0_pads[] = {
173 		NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL),
174 		NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL),
175 		NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL),
176 		NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL),
177 		NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL),
178 		NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL),
179 		NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL),
180 		NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL),
181 		NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL),
182 		NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL),
183 	};
184 
185 	imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads));
186 }
187 
188 static void setup_iomux_i2c(void)
189 {
190 	static const iomux_v3_cfg_t i2c0_pads[] = {
191 		VF610_PAD_PTB14__I2C0_SCL,
192 		VF610_PAD_PTB15__I2C0_SDA,
193 	};
194 
195 	imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads));
196 }
197 
198 #ifdef CONFIG_NAND_VF610_NFC
199 static void setup_iomux_nfc(void)
200 {
201 	static const iomux_v3_cfg_t nfc_pads[] = {
202 		VF610_PAD_PTD23__NF_IO7,
203 		VF610_PAD_PTD22__NF_IO6,
204 		VF610_PAD_PTD21__NF_IO5,
205 		VF610_PAD_PTD20__NF_IO4,
206 		VF610_PAD_PTD19__NF_IO3,
207 		VF610_PAD_PTD18__NF_IO2,
208 		VF610_PAD_PTD17__NF_IO1,
209 		VF610_PAD_PTD16__NF_IO0,
210 		VF610_PAD_PTB24__NF_WE_B,
211 		VF610_PAD_PTB25__NF_CE0_B,
212 		VF610_PAD_PTB27__NF_RE_B,
213 		VF610_PAD_PTC26__NF_RB_B,
214 		VF610_PAD_PTC27__NF_ALE,
215 		VF610_PAD_PTC28__NF_CLE
216 	};
217 
218 	imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads));
219 }
220 #endif
221 
222 #ifdef CONFIG_FSL_DSPI
223 static void setup_iomux_dspi(void)
224 {
225 	static const iomux_v3_cfg_t dspi1_pads[] = {
226 		VF610_PAD_PTD5__DSPI1_CS0,
227 		VF610_PAD_PTD6__DSPI1_SIN,
228 		VF610_PAD_PTD7__DSPI1_SOUT,
229 		VF610_PAD_PTD8__DSPI1_SCK,
230 	};
231 
232 	imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads));
233 }
234 #endif
235 
236 #ifdef CONFIG_VYBRID_GPIO
237 static void setup_iomux_gpio(void)
238 {
239 	static const iomux_v3_cfg_t gpio_pads[] = {
240 		VF610_PAD_PTA17__GPIO_7,
241 		VF610_PAD_PTA20__GPIO_10,
242 		VF610_PAD_PTA21__GPIO_11,
243 		VF610_PAD_PTA30__GPIO_20,
244 		VF610_PAD_PTA31__GPIO_21,
245 		VF610_PAD_PTB0__GPIO_22,
246 		VF610_PAD_PTB1__GPIO_23,
247 		VF610_PAD_PTB6__GPIO_28,
248 		VF610_PAD_PTB7__GPIO_29,
249 		VF610_PAD_PTB8__GPIO_30,
250 		VF610_PAD_PTB9__GPIO_31,
251 		VF610_PAD_PTB12__GPIO_34,
252 		VF610_PAD_PTB13__GPIO_35,
253 		VF610_PAD_PTB16__GPIO_38,
254 		VF610_PAD_PTB17__GPIO_39,
255 		VF610_PAD_PTB18__GPIO_40,
256 		VF610_PAD_PTB21__GPIO_43,
257 		VF610_PAD_PTB22__GPIO_44,
258 		VF610_PAD_PTC0__GPIO_45,
259 		VF610_PAD_PTC1__GPIO_46,
260 		VF610_PAD_PTC2__GPIO_47,
261 		VF610_PAD_PTC3__GPIO_48,
262 		VF610_PAD_PTC4__GPIO_49,
263 		VF610_PAD_PTC5__GPIO_50,
264 		VF610_PAD_PTC6__GPIO_51,
265 		VF610_PAD_PTC7__GPIO_52,
266 		VF610_PAD_PTC8__GPIO_53,
267 		VF610_PAD_PTD31__GPIO_63,
268 		VF610_PAD_PTD30__GPIO_64,
269 		VF610_PAD_PTD29__GPIO_65,
270 		VF610_PAD_PTD28__GPIO_66,
271 		VF610_PAD_PTD27__GPIO_67,
272 		VF610_PAD_PTD26__GPIO_68,
273 		VF610_PAD_PTD25__GPIO_69,
274 		VF610_PAD_PTD24__GPIO_70,
275 		VF610_PAD_PTD9__GPIO_88,
276 		VF610_PAD_PTD10__GPIO_89,
277 		VF610_PAD_PTD11__GPIO_90,
278 		VF610_PAD_PTD12__GPIO_91,
279 		VF610_PAD_PTD13__GPIO_92,
280 		VF610_PAD_PTB23__GPIO_93,
281 		VF610_PAD_PTB26__GPIO_96,
282 		VF610_PAD_PTB28__GPIO_98,
283 		VF610_PAD_PTC30__GPIO_103,
284 		VF610_PAD_PTA7__GPIO_134,
285 	};
286 
287 	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
288 }
289 #endif
290 
291 #ifdef CONFIG_VIDEO_FSL_DCU_FB
292 static void setup_iomux_fsl_dcu(void)
293 {
294 	static const iomux_v3_cfg_t dcu0_pads[] = {
295 		VF610_PAD_PTE0__DCU0_HSYNC,
296 		VF610_PAD_PTE1__DCU0_VSYNC,
297 		VF610_PAD_PTE2__DCU0_PCLK,
298 		VF610_PAD_PTE4__DCU0_DE,
299 		VF610_PAD_PTE5__DCU0_R0,
300 		VF610_PAD_PTE6__DCU0_R1,
301 		VF610_PAD_PTE7__DCU0_R2,
302 		VF610_PAD_PTE8__DCU0_R3,
303 		VF610_PAD_PTE9__DCU0_R4,
304 		VF610_PAD_PTE10__DCU0_R5,
305 		VF610_PAD_PTE11__DCU0_R6,
306 		VF610_PAD_PTE12__DCU0_R7,
307 		VF610_PAD_PTE13__DCU0_G0,
308 		VF610_PAD_PTE14__DCU0_G1,
309 		VF610_PAD_PTE15__DCU0_G2,
310 		VF610_PAD_PTE16__DCU0_G3,
311 		VF610_PAD_PTE17__DCU0_G4,
312 		VF610_PAD_PTE18__DCU0_G5,
313 		VF610_PAD_PTE19__DCU0_G6,
314 		VF610_PAD_PTE20__DCU0_G7,
315 		VF610_PAD_PTE21__DCU0_B0,
316 		VF610_PAD_PTE22__DCU0_B1,
317 		VF610_PAD_PTE23__DCU0_B2,
318 		VF610_PAD_PTE24__DCU0_B3,
319 		VF610_PAD_PTE25__DCU0_B4,
320 		VF610_PAD_PTE26__DCU0_B5,
321 		VF610_PAD_PTE27__DCU0_B6,
322 		VF610_PAD_PTE28__DCU0_B7,
323 	};
324 
325 	imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads));
326 }
327 
328 static void setup_tcon(void)
329 {
330 	setbits_le32(TCON0_BASE_ADDR, (1 << 29));
331 }
332 #endif
333 
334 #ifdef CONFIG_FSL_ESDHC
335 struct fsl_esdhc_cfg esdhc_cfg[1] = {
336 	{ESDHC1_BASE_ADDR},
337 };
338 
339 int board_mmc_getcd(struct mmc *mmc)
340 {
341 	/* eSDHC1 is always present */
342 	return 1;
343 }
344 
345 int board_mmc_init(bd_t *bis)
346 {
347 	static const iomux_v3_cfg_t esdhc1_pads[] = {
348 		NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL),
349 		NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL),
350 		NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL),
351 		NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL),
352 		NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL),
353 		NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL),
354 	};
355 
356 	esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
357 
358 	imx_iomux_v3_setup_multiple_pads(
359 		esdhc1_pads, ARRAY_SIZE(esdhc1_pads));
360 
361 	return fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
362 }
363 #endif
364 
365 static inline int is_colibri_vf61(void)
366 {
367 	struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR;
368 
369 	/*
370 	 * Detect board type by Level 2 Cache: VF50 don't have any
371 	 * Level 2 Cache.
372 	 */
373 	return !!mscm->cpxcfg1;
374 }
375 
376 static void clock_init(void)
377 {
378 	struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR;
379 	struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR;
380 	u32 pfd_clk_sel, ddr_clk_sel;
381 
382 	clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK,
383 			CCM_CCGR0_UART0_CTRL_MASK);
384 #ifdef CONFIG_FSL_DSPI
385 	setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK);
386 #endif
387 	clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK,
388 			CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK);
389 	clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK,
390 			CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK |
391 			CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK |
392 			CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK);
393 	clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK,
394 			CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK);
395 	clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK,
396 			CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK |
397 			CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK);
398 	clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK,
399 			CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK);
400 	clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK,
401 			CCM_CCGR7_SDHC1_CTRL_MASK);
402 	clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK,
403 			CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK);
404 	clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK,
405 			CCM_CCGR10_NFC_CTRL_MASK);
406 
407 #ifdef CONFIG_USB_EHCI_VF
408 	setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK);
409 	setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK);
410 
411 	clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS |
412 			ANADIG_PLL3_CTRL_POWERDOWN |
413 			ANADIG_PLL3_CTRL_DIV_SELECT,
414 			ANADIG_PLL3_CTRL_ENABLE);
415 	clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS |
416 			ANADIG_PLL7_CTRL_POWERDOWN |
417 			ANADIG_PLL7_CTRL_DIV_SELECT,
418 			ANADIG_PLL7_CTRL_ENABLE);
419 #endif
420 
421 	clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS |
422 			ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE |
423 			ANADIG_PLL5_CTRL_DIV_SELECT);
424 
425 	if (is_colibri_vf61()) {
426 		clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS |
427 				ANADIG_PLL2_CTRL_POWERDOWN,
428 				ANADIG_PLL2_CTRL_ENABLE |
429 				ANADIG_PLL2_CTRL_DIV_SELECT);
430 	}
431 
432 	clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN,
433 			ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT);
434 
435 	clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK,
436 			CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5));
437 
438 	/* See "Typical PLL Configuration" */
439 	if (is_colibri_vf61()) {
440 		pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1);
441 		ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0);
442 	} else {
443 		pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3);
444 		ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1);
445 	}
446 
447 	clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel |
448 			CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN |
449 			CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN |
450 			CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN |
451 			CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN |
452 			ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) |
453 			CCM_CCSR_SYS_CLK_SEL(4));
454 
455 	clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK,
456 			CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) |
457 			CCM_CACRR_ARM_CLK_DIV(0));
458 	clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK,
459 			CCM_CSCMR1_ESDHC1_CLK_SEL(3) |
460 			CCM_CSCMR1_NFC_CLK_SEL(0));
461 	clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK,
462 			CCM_CSCDR1_RMII_CLK_EN);
463 	clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK,
464 			CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) |
465 			CCM_CSCDR2_NFC_EN);
466 	clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK,
467 			CCM_CSCDR3_NFC_PRE_DIV(3));
468 	clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK,
469 			CCM_CSCMR2_RMII_CLK_SEL(2));
470 
471 #ifdef CONFIG_VIDEO_FSL_DCU_FB
472 		setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK);
473 		setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK);
474 #endif
475 }
476 
477 static void mscm_init(void)
478 {
479 	struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR;
480 	int i;
481 
482 	for (i = 0; i < MSCM_IRSPRC_NUM; i++)
483 		writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]);
484 }
485 
486 int board_phy_config(struct phy_device *phydev)
487 {
488 	if (phydev->drv->config)
489 		phydev->drv->config(phydev);
490 
491 	return 0;
492 }
493 
494 int board_early_init_f(void)
495 {
496 	clock_init();
497 	mscm_init();
498 
499 	setup_iomux_uart();
500 	setup_iomux_enet();
501 	setup_iomux_i2c();
502 #ifdef CONFIG_NAND_VF610_NFC
503 	setup_iomux_nfc();
504 #endif
505 
506 #ifdef CONFIG_VYBRID_GPIO
507 	setup_iomux_gpio();
508 #endif
509 
510 #ifdef CONFIG_FSL_DSPI
511 	setup_iomux_dspi();
512 #endif
513 
514 #ifdef CONFIG_VIDEO_FSL_DCU_FB
515 	setup_tcon();
516 	setup_iomux_fsl_dcu();
517 #endif
518 
519 	return 0;
520 }
521 
522 #ifdef CONFIG_BOARD_LATE_INIT
523 int board_late_init(void)
524 {
525 	struct src *src = (struct src *)SRC_BASE_ADDR;
526 
527 	if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT)
528 			== SRC_SBMR2_BMOD_SERIAL) {
529 		printf("Serial Downloader recovery mode, disable autoboot\n");
530 		env_set("bootdelay", "-1");
531 	}
532 
533 	return 0;
534 }
535 #endif /* CONFIG_BOARD_LATE_INIT */
536 
537 int board_init(void)
538 {
539 	struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR;
540 
541 	/* address of boot parameters */
542 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
543 
544 	/*
545 	 * Enable external 32K Oscillator
546 	 *
547 	 * The internal clock experiences significant drift
548 	 * so we must use the external oscillator in order
549 	 * to maintain correct time in the hwclock
550 	 */
551 
552 	setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN);
553 
554 #ifdef CONFIG_USB_EHCI_VF
555 	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
556 #endif
557 
558 	return 0;
559 }
560 
561 int checkboard(void)
562 {
563 	if (is_colibri_vf61())
564 		puts("Board: Colibri VF61\n");
565 	else
566 		puts("Board: Colibri VF50\n");
567 
568 	return 0;
569 }
570 
571 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
572 int ft_board_setup(void *blob, bd_t *bd)
573 {
574 	int ret = 0;
575 #ifdef CONFIG_FDT_FIXUP_PARTITIONS
576 	static const struct node_info nodes[] = {
577 		{ "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */
578 	};
579 
580 	/* Update partition nodes using info from mtdparts env var */
581 	puts("   Updating MTD partitions...\n");
582 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
583 #endif
584 #ifdef CONFIG_VIDEO_FSL_DCU_FB
585 	ret = fsl_dcu_fixedfb_setup(blob);
586 	if (ret)
587 		return ret;
588 #endif
589 
590 	return ft_common_board_setup(blob, bd);
591 }
592 #endif
593 
594 #ifdef CONFIG_USB_EHCI_VF
595 int board_ehci_hcd_init(int port)
596 {
597 	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
598 
599 	switch (port) {
600 	case 0:
601 		/* USBC does not have PEN, also configured as USB client only */
602 		break;
603 	case 1:
604 		gpio_request(USB_PEN_GPIO, "usb-pen-gpio");
605 		gpio_direction_output(USB_PEN_GPIO, 0);
606 		break;
607 	}
608 	return 0;
609 }
610 
611 int board_usb_phy_mode(int port)
612 {
613 	switch (port) {
614 	case 0:
615 		/*
616 		 * Port 0 is used only in client mode on Colibri Vybrid modules
617 		 * Check for state of USB client gpio pin and accordingly return
618 		 * USB_INIT_DEVICE or USB_INIT_HOST.
619 		 */
620 		if (gpio_get_value(USB_CDET_GPIO))
621 			return USB_INIT_DEVICE;
622 		else
623 			return USB_INIT_HOST;
624 	case 1:
625 		/* Port 1 is used only in host mode on Colibri Vybrid modules */
626 		return USB_INIT_HOST;
627 	default:
628 		/*
629 		 * There are only two USB controllers on Vybrid. Ideally we will
630 		 * not reach here. However return USB_INIT_HOST if we do.
631 		 */
632 		return USB_INIT_HOST;
633 	}
634 }
635 #endif
636 
637 /*
638  * Backlight off before OS handover
639  */
640 void board_preboot_os(void)
641 {
642 	gpio_request(PTC0_GPIO_45, "BL_ON");
643 	gpio_direction_output(PTC0_GPIO_45, 0);
644 }
645