1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright 2015 Toradex, Inc. 4 * 5 * Based on vf610twr.c: 6 * Copyright 2013 Freescale Semiconductor, Inc. 7 */ 8 9 #include <common.h> 10 #include <asm/io.h> 11 #include <asm/arch/imx-regs.h> 12 #include <asm/arch/iomux-vf610.h> 13 #include <asm/arch/ddrmc-vf610.h> 14 #include <asm/arch/crm_regs.h> 15 #include <asm/arch/clock.h> 16 #include <mmc.h> 17 #include <fdt_support.h> 18 #include <fsl_esdhc.h> 19 #include <fsl_dcu_fb.h> 20 #include <jffs2/load_kernel.h> 21 #include <miiphy.h> 22 #include <mtd_node.h> 23 #include <netdev.h> 24 #include <i2c.h> 25 #include <g_dnl.h> 26 #include <asm/gpio.h> 27 #include <usb.h> 28 #include "../common/tdx-common.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ 33 PAD_CTL_DSE_25ohm | PAD_CTL_OBE_IBE_ENABLE) 34 35 #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ 36 PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) 37 38 #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ 39 PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) 40 41 #define USB_PEN_GPIO 83 42 #define USB_CDET_GPIO 102 43 44 static struct ddrmc_cr_setting colibri_vf_cr_settings[] = { 45 /* AXI */ 46 { DDRMC_CR117_AXI0_W_PRI(0) | DDRMC_CR117_AXI0_R_PRI(0), 117 }, 47 { DDRMC_CR118_AXI1_W_PRI(1) | DDRMC_CR118_AXI1_R_PRI(1), 118 }, 48 { DDRMC_CR120_AXI0_PRI1_RPRI(2) | 49 DDRMC_CR120_AXI0_PRI0_RPRI(2), 120 }, 50 { DDRMC_CR121_AXI0_PRI3_RPRI(2) | 51 DDRMC_CR121_AXI0_PRI2_RPRI(2), 121 }, 52 { DDRMC_CR122_AXI1_PRI1_RPRI(1) | DDRMC_CR122_AXI1_PRI0_RPRI(1) | 53 DDRMC_CR122_AXI0_PRIRLX(100), 122 }, 54 { DDRMC_CR123_AXI1_P_ODR_EN | DDRMC_CR123_AXI1_PRI3_RPRI(1) | 55 DDRMC_CR123_AXI1_PRI2_RPRI(1), 123 }, 56 { DDRMC_CR124_AXI1_PRIRLX(100), 124 }, 57 { DDRMC_CR126_PHY_RDLAT(8), 126 }, 58 { DDRMC_CR132_WRLAT_ADJ(5) | 59 DDRMC_CR132_RDLAT_ADJ(6), 132 }, 60 { DDRMC_CR137_PHYCTL_DL(2), 137 }, 61 { DDRMC_CR138_PHY_WRLV_MXDL(256) | 62 DDRMC_CR138_PHYDRAM_CK_EN(1), 138 }, 63 { DDRMC_CR139_PHY_WRLV_RESPLAT(4) | DDRMC_CR139_PHY_WRLV_LOAD(7) | 64 DDRMC_CR139_PHY_WRLV_DLL(3) | 65 DDRMC_CR139_PHY_WRLV_EN(3), 139 }, 66 { DDRMC_CR140_PHY_WRLV_WW(64), 140 }, 67 { DDRMC_CR143_RDLV_GAT_MXDL(1536) | 68 DDRMC_CR143_RDLV_MXDL(128), 143 }, 69 { DDRMC_CR144_PHY_RDLVL_RES(4) | DDRMC_CR144_PHY_RDLV_LOAD(7) | 70 DDRMC_CR144_PHY_RDLV_DLL(3) | 71 DDRMC_CR144_PHY_RDLV_EN(3), 144 }, 72 { DDRMC_CR145_PHY_RDLV_RR(64), 145 }, 73 { DDRMC_CR146_PHY_RDLVL_RESP(64), 146 }, 74 { DDRMC_CR147_RDLV_RESP_MASK(983040), 147 }, 75 { DDRMC_CR148_RDLV_GATE_RESP_MASK(983040), 148 }, 76 { DDRMC_CR151_RDLV_GAT_DQ_ZERO_CNT(1) | 77 DDRMC_CR151_RDLVL_DQ_ZERO_CNT(1), 151 }, 78 79 { DDRMC_CR154_PAD_ZQ_EARLY_CMP_EN_TIMER(13) | 80 DDRMC_CR154_PAD_ZQ_MODE(1) | 81 DDRMC_CR154_DDR_SEL_PAD_CONTR(3) | 82 DDRMC_CR154_PAD_ZQ_HW_FOR(1), 154 }, 83 { DDRMC_CR155_PAD_ODT_BYTE1(2) | DDRMC_CR155_PAD_ODT_BYTE0(2), 155 }, 84 { DDRMC_CR158_TWR(6), 158 }, 85 { DDRMC_CR161_ODT_EN(1) | DDRMC_CR161_TODTH_RD(2) | 86 DDRMC_CR161_TODTH_WR(2), 161 }, 87 /* end marker */ 88 { 0, -1 } 89 }; 90 91 static const iomux_v3_cfg_t usb_pads[] = { 92 VF610_PAD_PTD4__GPIO_83, 93 VF610_PAD_PTC29__GPIO_102, 94 }; 95 96 int dram_init(void) 97 { 98 static const struct ddr3_jedec_timings timings = { 99 .tinit = 5, 100 .trst_pwron = 80000, 101 .cke_inactive = 200000, 102 .wrlat = 5, 103 .caslat_lin = 12, 104 .trc = 21, 105 .trrd = 4, 106 .tccd = 4, 107 .tbst_int_interval = 0, 108 .tfaw = 20, 109 .trp = 6, 110 .twtr = 4, 111 .tras_min = 15, 112 .tmrd = 4, 113 .trtp = 4, 114 .tras_max = 28080, 115 .tmod = 12, 116 .tckesr = 4, 117 .tcke = 3, 118 .trcd_int = 6, 119 .tras_lockout = 0, 120 .tdal = 12, 121 .bstlen = 3, 122 .tdll = 512, 123 .trp_ab = 6, 124 .tref = 3120, 125 .trfc = 64, 126 .tref_int = 0, 127 .tpdex = 3, 128 .txpdll = 10, 129 .txsnr = 48, 130 .txsr = 468, 131 .cksrx = 5, 132 .cksre = 5, 133 .freq_chg_en = 0, 134 .zqcl = 256, 135 .zqinit = 512, 136 .zqcs = 64, 137 .ref_per_zq = 64, 138 .zqcs_rotate = 0, 139 .aprebit = 10, 140 .cmd_age_cnt = 64, 141 .age_cnt = 64, 142 .q_fullness = 7, 143 .odt_rd_mapcs0 = 0, 144 .odt_wr_mapcs0 = 1, 145 .wlmrd = 40, 146 .wldqsen = 25, 147 }; 148 149 ddrmc_setup_iomux(NULL, 0); 150 151 ddrmc_ctrl_init_ddr3(&timings, colibri_vf_cr_settings, NULL, 1, 2); 152 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 153 154 return 0; 155 } 156 157 static void setup_iomux_uart(void) 158 { 159 static const iomux_v3_cfg_t uart_pads[] = { 160 NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, UART_PAD_CTRL), 161 NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, UART_PAD_CTRL), 162 NEW_PAD_CTRL(VF610_PAD_PTB10__UART0_TX, UART_PAD_CTRL), 163 NEW_PAD_CTRL(VF610_PAD_PTB11__UART0_RX, UART_PAD_CTRL), 164 }; 165 166 imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); 167 } 168 169 static void setup_iomux_enet(void) 170 { 171 static const iomux_v3_cfg_t enet0_pads[] = { 172 NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKOUT, ENET_PAD_CTRL), 173 NEW_PAD_CTRL(VF610_PAD_PTC10__RMII1_MDIO, ENET_PAD_CTRL), 174 NEW_PAD_CTRL(VF610_PAD_PTC9__RMII1_MDC, ENET_PAD_CTRL), 175 NEW_PAD_CTRL(VF610_PAD_PTC11__RMII1_CRS_DV, ENET_PAD_CTRL), 176 NEW_PAD_CTRL(VF610_PAD_PTC12__RMII1_RD1, ENET_PAD_CTRL), 177 NEW_PAD_CTRL(VF610_PAD_PTC13__RMII1_RD0, ENET_PAD_CTRL), 178 NEW_PAD_CTRL(VF610_PAD_PTC14__RMII1_RXER, ENET_PAD_CTRL), 179 NEW_PAD_CTRL(VF610_PAD_PTC15__RMII1_TD1, ENET_PAD_CTRL), 180 NEW_PAD_CTRL(VF610_PAD_PTC16__RMII1_TD0, ENET_PAD_CTRL), 181 NEW_PAD_CTRL(VF610_PAD_PTC17__RMII1_TXEN, ENET_PAD_CTRL), 182 }; 183 184 imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); 185 } 186 187 static void setup_iomux_i2c(void) 188 { 189 static const iomux_v3_cfg_t i2c0_pads[] = { 190 VF610_PAD_PTB14__I2C0_SCL, 191 VF610_PAD_PTB15__I2C0_SDA, 192 }; 193 194 imx_iomux_v3_setup_multiple_pads(i2c0_pads, ARRAY_SIZE(i2c0_pads)); 195 } 196 197 #ifdef CONFIG_NAND_VF610_NFC 198 static void setup_iomux_nfc(void) 199 { 200 static const iomux_v3_cfg_t nfc_pads[] = { 201 VF610_PAD_PTD23__NF_IO7, 202 VF610_PAD_PTD22__NF_IO6, 203 VF610_PAD_PTD21__NF_IO5, 204 VF610_PAD_PTD20__NF_IO4, 205 VF610_PAD_PTD19__NF_IO3, 206 VF610_PAD_PTD18__NF_IO2, 207 VF610_PAD_PTD17__NF_IO1, 208 VF610_PAD_PTD16__NF_IO0, 209 VF610_PAD_PTB24__NF_WE_B, 210 VF610_PAD_PTB25__NF_CE0_B, 211 VF610_PAD_PTB27__NF_RE_B, 212 VF610_PAD_PTC26__NF_RB_B, 213 VF610_PAD_PTC27__NF_ALE, 214 VF610_PAD_PTC28__NF_CLE 215 }; 216 217 imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); 218 } 219 #endif 220 221 #ifdef CONFIG_FSL_DSPI 222 static void setup_iomux_dspi(void) 223 { 224 static const iomux_v3_cfg_t dspi1_pads[] = { 225 VF610_PAD_PTD5__DSPI1_CS0, 226 VF610_PAD_PTD6__DSPI1_SIN, 227 VF610_PAD_PTD7__DSPI1_SOUT, 228 VF610_PAD_PTD8__DSPI1_SCK, 229 }; 230 231 imx_iomux_v3_setup_multiple_pads(dspi1_pads, ARRAY_SIZE(dspi1_pads)); 232 } 233 #endif 234 235 #ifdef CONFIG_VYBRID_GPIO 236 static void setup_iomux_gpio(void) 237 { 238 static const iomux_v3_cfg_t gpio_pads[] = { 239 VF610_PAD_PTA17__GPIO_7, 240 VF610_PAD_PTA20__GPIO_10, 241 VF610_PAD_PTA21__GPIO_11, 242 VF610_PAD_PTA30__GPIO_20, 243 VF610_PAD_PTA31__GPIO_21, 244 VF610_PAD_PTB0__GPIO_22, 245 VF610_PAD_PTB1__GPIO_23, 246 VF610_PAD_PTB6__GPIO_28, 247 VF610_PAD_PTB7__GPIO_29, 248 VF610_PAD_PTB8__GPIO_30, 249 VF610_PAD_PTB9__GPIO_31, 250 VF610_PAD_PTB12__GPIO_34, 251 VF610_PAD_PTB13__GPIO_35, 252 VF610_PAD_PTB16__GPIO_38, 253 VF610_PAD_PTB17__GPIO_39, 254 VF610_PAD_PTB18__GPIO_40, 255 VF610_PAD_PTB21__GPIO_43, 256 VF610_PAD_PTB22__GPIO_44, 257 VF610_PAD_PTC0__GPIO_45, 258 VF610_PAD_PTC1__GPIO_46, 259 VF610_PAD_PTC2__GPIO_47, 260 VF610_PAD_PTC3__GPIO_48, 261 VF610_PAD_PTC4__GPIO_49, 262 VF610_PAD_PTC5__GPIO_50, 263 VF610_PAD_PTC6__GPIO_51, 264 VF610_PAD_PTC7__GPIO_52, 265 VF610_PAD_PTC8__GPIO_53, 266 VF610_PAD_PTD31__GPIO_63, 267 VF610_PAD_PTD30__GPIO_64, 268 VF610_PAD_PTD29__GPIO_65, 269 VF610_PAD_PTD28__GPIO_66, 270 VF610_PAD_PTD27__GPIO_67, 271 VF610_PAD_PTD26__GPIO_68, 272 VF610_PAD_PTD25__GPIO_69, 273 VF610_PAD_PTD24__GPIO_70, 274 VF610_PAD_PTD9__GPIO_88, 275 VF610_PAD_PTD10__GPIO_89, 276 VF610_PAD_PTD11__GPIO_90, 277 VF610_PAD_PTD12__GPIO_91, 278 VF610_PAD_PTD13__GPIO_92, 279 VF610_PAD_PTB23__GPIO_93, 280 VF610_PAD_PTB26__GPIO_96, 281 VF610_PAD_PTB28__GPIO_98, 282 VF610_PAD_PTC30__GPIO_103, 283 VF610_PAD_PTA7__GPIO_134, 284 }; 285 286 imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); 287 } 288 #endif 289 290 #ifdef CONFIG_VIDEO_FSL_DCU_FB 291 static void setup_iomux_fsl_dcu(void) 292 { 293 static const iomux_v3_cfg_t dcu0_pads[] = { 294 VF610_PAD_PTE0__DCU0_HSYNC, 295 VF610_PAD_PTE1__DCU0_VSYNC, 296 VF610_PAD_PTE2__DCU0_PCLK, 297 VF610_PAD_PTE4__DCU0_DE, 298 VF610_PAD_PTE5__DCU0_R0, 299 VF610_PAD_PTE6__DCU0_R1, 300 VF610_PAD_PTE7__DCU0_R2, 301 VF610_PAD_PTE8__DCU0_R3, 302 VF610_PAD_PTE9__DCU0_R4, 303 VF610_PAD_PTE10__DCU0_R5, 304 VF610_PAD_PTE11__DCU0_R6, 305 VF610_PAD_PTE12__DCU0_R7, 306 VF610_PAD_PTE13__DCU0_G0, 307 VF610_PAD_PTE14__DCU0_G1, 308 VF610_PAD_PTE15__DCU0_G2, 309 VF610_PAD_PTE16__DCU0_G3, 310 VF610_PAD_PTE17__DCU0_G4, 311 VF610_PAD_PTE18__DCU0_G5, 312 VF610_PAD_PTE19__DCU0_G6, 313 VF610_PAD_PTE20__DCU0_G7, 314 VF610_PAD_PTE21__DCU0_B0, 315 VF610_PAD_PTE22__DCU0_B1, 316 VF610_PAD_PTE23__DCU0_B2, 317 VF610_PAD_PTE24__DCU0_B3, 318 VF610_PAD_PTE25__DCU0_B4, 319 VF610_PAD_PTE26__DCU0_B5, 320 VF610_PAD_PTE27__DCU0_B6, 321 VF610_PAD_PTE28__DCU0_B7, 322 }; 323 324 imx_iomux_v3_setup_multiple_pads(dcu0_pads, ARRAY_SIZE(dcu0_pads)); 325 } 326 327 static void setup_tcon(void) 328 { 329 setbits_le32(TCON0_BASE_ADDR, (1 << 29)); 330 } 331 #endif 332 333 #ifdef CONFIG_FSL_ESDHC 334 struct fsl_esdhc_cfg esdhc_cfg[1] = { 335 {ESDHC1_BASE_ADDR}, 336 }; 337 338 int board_mmc_getcd(struct mmc *mmc) 339 { 340 /* eSDHC1 is always present */ 341 return 1; 342 } 343 344 int board_mmc_init(bd_t *bis) 345 { 346 static const iomux_v3_cfg_t esdhc1_pads[] = { 347 NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), 348 NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), 349 NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), 350 NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), 351 NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), 352 NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), 353 }; 354 355 esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 356 357 imx_iomux_v3_setup_multiple_pads( 358 esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); 359 360 return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); 361 } 362 #endif 363 364 static inline int is_colibri_vf61(void) 365 { 366 struct mscm *mscm = (struct mscm *)MSCM_BASE_ADDR; 367 368 /* 369 * Detect board type by Level 2 Cache: VF50 don't have any 370 * Level 2 Cache. 371 */ 372 return !!mscm->cpxcfg1; 373 } 374 375 static void clock_init(void) 376 { 377 struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; 378 struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; 379 u32 pfd_clk_sel, ddr_clk_sel; 380 381 clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, 382 CCM_CCGR0_UART0_CTRL_MASK); 383 #ifdef CONFIG_FSL_DSPI 384 setbits_le32(&ccm->ccgr0, CCM_CCGR0_DSPI1_CTRL_MASK); 385 #endif 386 clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, 387 CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); 388 clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, 389 CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | 390 CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | 391 CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK); 392 clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, 393 CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); 394 clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, 395 CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | 396 CCM_CCGR4_GPC_CTRL_MASK | CCM_CCGR4_I2C0_CTRL_MASK); 397 clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, 398 CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); 399 clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, 400 CCM_CCGR7_SDHC1_CTRL_MASK); 401 clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, 402 CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); 403 clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, 404 CCM_CCGR10_NFC_CTRL_MASK); 405 406 #ifdef CONFIG_USB_EHCI_VF 407 setbits_le32(&ccm->ccgr1, CCM_CCGR1_USBC0_CTRL_MASK); 408 setbits_le32(&ccm->ccgr7, CCM_CCGR7_USBC1_CTRL_MASK); 409 410 clrsetbits_le32(&anadig->pll3_ctrl, ANADIG_PLL3_CTRL_BYPASS | 411 ANADIG_PLL3_CTRL_POWERDOWN | 412 ANADIG_PLL3_CTRL_DIV_SELECT, 413 ANADIG_PLL3_CTRL_ENABLE); 414 clrsetbits_le32(&anadig->pll7_ctrl, ANADIG_PLL7_CTRL_BYPASS | 415 ANADIG_PLL7_CTRL_POWERDOWN | 416 ANADIG_PLL7_CTRL_DIV_SELECT, 417 ANADIG_PLL7_CTRL_ENABLE); 418 #endif 419 420 clrsetbits_le32(&anadig->pll5_ctrl, ANADIG_PLL5_CTRL_BYPASS | 421 ANADIG_PLL5_CTRL_POWERDOWN, ANADIG_PLL5_CTRL_ENABLE | 422 ANADIG_PLL5_CTRL_DIV_SELECT); 423 424 if (is_colibri_vf61()) { 425 clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL5_CTRL_BYPASS | 426 ANADIG_PLL2_CTRL_POWERDOWN, 427 ANADIG_PLL2_CTRL_ENABLE | 428 ANADIG_PLL2_CTRL_DIV_SELECT); 429 } 430 431 clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, 432 ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); 433 434 clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, 435 CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); 436 437 /* See "Typical PLL Configuration" */ 438 if (is_colibri_vf61()) { 439 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(1); 440 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(0); 441 } else { 442 pfd_clk_sel = CCM_CCSR_PLL1_PFD_CLK_SEL(3); 443 ddr_clk_sel = CCM_CCSR_DDRC_CLK_SEL(1); 444 } 445 446 clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, pfd_clk_sel | 447 CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | 448 CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | 449 CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | 450 CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | 451 ddr_clk_sel | CCM_CCSR_FAST_CLK_SEL(1) | 452 CCM_CCSR_SYS_CLK_SEL(4)); 453 454 clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, 455 CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | 456 CCM_CACRR_ARM_CLK_DIV(0)); 457 clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, 458 CCM_CSCMR1_ESDHC1_CLK_SEL(3) | 459 CCM_CSCMR1_NFC_CLK_SEL(0)); 460 clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, 461 CCM_CSCDR1_RMII_CLK_EN); 462 clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, 463 CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | 464 CCM_CSCDR2_NFC_EN); 465 clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, 466 CCM_CSCDR3_NFC_PRE_DIV(3)); 467 clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, 468 CCM_CSCMR2_RMII_CLK_SEL(2)); 469 470 #ifdef CONFIG_VIDEO_FSL_DCU_FB 471 setbits_le32(&ccm->ccgr1, CCM_CCGR1_TCON0_CTRL_MASK); 472 setbits_le32(&ccm->ccgr3, CCM_CCGR3_DCU0_CTRL_MASK); 473 #endif 474 } 475 476 static void mscm_init(void) 477 { 478 struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; 479 int i; 480 481 for (i = 0; i < MSCM_IRSPRC_NUM; i++) 482 writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); 483 } 484 485 int board_phy_config(struct phy_device *phydev) 486 { 487 if (phydev->drv->config) 488 phydev->drv->config(phydev); 489 490 return 0; 491 } 492 493 int board_early_init_f(void) 494 { 495 clock_init(); 496 mscm_init(); 497 498 setup_iomux_uart(); 499 setup_iomux_enet(); 500 setup_iomux_i2c(); 501 #ifdef CONFIG_NAND_VF610_NFC 502 setup_iomux_nfc(); 503 #endif 504 505 #ifdef CONFIG_VYBRID_GPIO 506 setup_iomux_gpio(); 507 #endif 508 509 #ifdef CONFIG_FSL_DSPI 510 setup_iomux_dspi(); 511 #endif 512 513 #ifdef CONFIG_VIDEO_FSL_DCU_FB 514 setup_tcon(); 515 setup_iomux_fsl_dcu(); 516 #endif 517 518 return 0; 519 } 520 521 #ifdef CONFIG_BOARD_LATE_INIT 522 int board_late_init(void) 523 { 524 struct src *src = (struct src *)SRC_BASE_ADDR; 525 526 if (((src->sbmr2 & SRC_SBMR2_BMOD_MASK) >> SRC_SBMR2_BMOD_SHIFT) 527 == SRC_SBMR2_BMOD_SERIAL) { 528 printf("Serial Downloader recovery mode, disable autoboot\n"); 529 env_set("bootdelay", "-1"); 530 } 531 532 return 0; 533 } 534 #endif /* CONFIG_BOARD_LATE_INIT */ 535 536 int board_init(void) 537 { 538 struct scsc_reg *scsc = (struct scsc_reg *)SCSC_BASE_ADDR; 539 540 /* address of boot parameters */ 541 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 542 543 /* 544 * Enable external 32K Oscillator 545 * 546 * The internal clock experiences significant drift 547 * so we must use the external oscillator in order 548 * to maintain correct time in the hwclock 549 */ 550 551 setbits_le32(&scsc->sosc_ctr, SCSC_SOSC_CTR_SOSC_EN); 552 553 #ifdef CONFIG_USB_EHCI_VF 554 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); 555 #endif 556 557 return 0; 558 } 559 560 int checkboard(void) 561 { 562 if (is_colibri_vf61()) 563 puts("Board: Colibri VF61\n"); 564 else 565 puts("Board: Colibri VF50\n"); 566 567 return 0; 568 } 569 570 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 571 int ft_board_setup(void *blob, bd_t *bd) 572 { 573 int ret = 0; 574 #ifdef CONFIG_FDT_FIXUP_PARTITIONS 575 static const struct node_info nodes[] = { 576 { "fsl,vf610-nfc", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 577 }; 578 579 /* Update partition nodes using info from mtdparts env var */ 580 puts(" Updating MTD partitions...\n"); 581 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 582 #endif 583 #ifdef CONFIG_VIDEO_FSL_DCU_FB 584 ret = fsl_dcu_fixedfb_setup(blob); 585 if (ret) 586 return ret; 587 #endif 588 589 return ft_common_board_setup(blob, bd); 590 } 591 #endif 592 593 #ifdef CONFIG_USB_EHCI_VF 594 int board_ehci_hcd_init(int port) 595 { 596 imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads)); 597 598 switch (port) { 599 case 0: 600 /* USBC does not have PEN, also configured as USB client only */ 601 break; 602 case 1: 603 gpio_request(USB_PEN_GPIO, "usb-pen-gpio"); 604 gpio_direction_output(USB_PEN_GPIO, 0); 605 break; 606 } 607 return 0; 608 } 609 610 int board_usb_phy_mode(int port) 611 { 612 switch (port) { 613 case 0: 614 /* 615 * Port 0 is used only in client mode on Colibri Vybrid modules 616 * Check for state of USB client gpio pin and accordingly return 617 * USB_INIT_DEVICE or USB_INIT_HOST. 618 */ 619 if (gpio_get_value(USB_CDET_GPIO)) 620 return USB_INIT_DEVICE; 621 else 622 return USB_INIT_HOST; 623 case 1: 624 /* Port 1 is used only in host mode on Colibri Vybrid modules */ 625 return USB_INIT_HOST; 626 default: 627 /* 628 * There are only two USB controllers on Vybrid. Ideally we will 629 * not reach here. However return USB_INIT_HOST if we do. 630 */ 631 return USB_INIT_HOST; 632 } 633 } 634 #endif 635