1*e57c6e5bSMarcel Ziswiler /* 2*e57c6e5bSMarcel Ziswiler * Copyright (C) 2012 Lucas Stach 3*e57c6e5bSMarcel Ziswiler * 4*e57c6e5bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 5*e57c6e5bSMarcel Ziswiler */ 6*e57c6e5bSMarcel Ziswiler 7*e57c6e5bSMarcel Ziswiler #include <common.h> 8*e57c6e5bSMarcel Ziswiler #include <asm/arch/clock.h> 9*e57c6e5bSMarcel Ziswiler #include <asm/arch/funcmux.h> 10*e57c6e5bSMarcel Ziswiler #include <asm/arch/pinmux.h> 11*e57c6e5bSMarcel Ziswiler #include <asm/arch-tegra/board.h> 12*e57c6e5bSMarcel Ziswiler #include <asm/gpio.h> 13*e57c6e5bSMarcel Ziswiler 14*e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_MMC 15*e57c6e5bSMarcel Ziswiler /* 16*e57c6e5bSMarcel Ziswiler * Routine: pin_mux_mmc 17*e57c6e5bSMarcel Ziswiler * Description: setup the pin muxes/tristate values for the SDMMC(s) 18*e57c6e5bSMarcel Ziswiler */ 19*e57c6e5bSMarcel Ziswiler void pin_mux_mmc(void) 20*e57c6e5bSMarcel Ziswiler { 21*e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); 22*e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GMB); 23*e57c6e5bSMarcel Ziswiler } 24*e57c6e5bSMarcel Ziswiler #endif 25*e57c6e5bSMarcel Ziswiler 26*e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_NAND 27*e57c6e5bSMarcel Ziswiler void pin_mux_nand(void) 28*e57c6e5bSMarcel Ziswiler { 29*e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); 30*e57c6e5bSMarcel Ziswiler } 31*e57c6e5bSMarcel Ziswiler #endif 32*e57c6e5bSMarcel Ziswiler 33*e57c6e5bSMarcel Ziswiler #ifdef CONFIG_USB_EHCI_TEGRA 34*e57c6e5bSMarcel Ziswiler void pin_mux_usb(void) 35*e57c6e5bSMarcel Ziswiler { 36*e57c6e5bSMarcel Ziswiler /* module internal USB bus to connect ethernet chipset */ 37*e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); 38*e57c6e5bSMarcel Ziswiler 39*e57c6e5bSMarcel Ziswiler /* ULPI reference clock output */ 40*e57c6e5bSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); 41*e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_CDEV2); 42*e57c6e5bSMarcel Ziswiler 43*e57c6e5bSMarcel Ziswiler /* PHY reset GPIO */ 44*e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_UAC); 45*e57c6e5bSMarcel Ziswiler 46*e57c6e5bSMarcel Ziswiler /* VBus GPIO */ 47*e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_DTE); 48*e57c6e5bSMarcel Ziswiler 49*e57c6e5bSMarcel Ziswiler /* USB 1 aka Tegra USB port 3 VBus */ 50*e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_SPIG); 51*e57c6e5bSMarcel Ziswiler } 52*e57c6e5bSMarcel Ziswiler #endif 53