1e57c6e5bSMarcel Ziswiler /* 2e57c6e5bSMarcel Ziswiler * Copyright (C) 2012 Lucas Stach 3e57c6e5bSMarcel Ziswiler * 4e57c6e5bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 5e57c6e5bSMarcel Ziswiler */ 6e57c6e5bSMarcel Ziswiler 7e57c6e5bSMarcel Ziswiler #include <common.h> 8e57c6e5bSMarcel Ziswiler #include <asm/arch/clock.h> 9e57c6e5bSMarcel Ziswiler #include <asm/arch/funcmux.h> 10e57c6e5bSMarcel Ziswiler #include <asm/arch/pinmux.h> 11a5825625SMarcel Ziswiler #include <asm/arch-tegra/ap.h> 12e57c6e5bSMarcel Ziswiler #include <asm/arch-tegra/board.h> 13a5825625SMarcel Ziswiler #include <asm/arch-tegra/tegra.h> 14e57c6e5bSMarcel Ziswiler #include <asm/gpio.h> 15a5825625SMarcel Ziswiler #include <asm/io.h> 1610ef82d3SMarcel Ziswiler #include <i2c.h> 1710ef82d3SMarcel Ziswiler 1810ef82d3SMarcel Ziswiler #define PMU_I2C_ADDRESS 0x34 1910ef82d3SMarcel Ziswiler #define MAX_I2C_RETRY 3 2010ef82d3SMarcel Ziswiler #define PMU_SUPPLYENE 0x14 2110ef82d3SMarcel Ziswiler #define PMU_SUPPLYENE_SYSINEN (1<<5) 2210ef82d3SMarcel Ziswiler #define PMU_SUPPLYENE_EXITSLREQ (1<<1) 23a5825625SMarcel Ziswiler 24a5825625SMarcel Ziswiler int arch_misc_init(void) 25a5825625SMarcel Ziswiler { 2610ef82d3SMarcel Ziswiler /* Disable PMIC sleep mode on low supply voltage */ 2710ef82d3SMarcel Ziswiler struct udevice *dev; 2810ef82d3SMarcel Ziswiler u8 addr, data[1]; 2910ef82d3SMarcel Ziswiler int err; 3010ef82d3SMarcel Ziswiler 3110ef82d3SMarcel Ziswiler err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); 3210ef82d3SMarcel Ziswiler if (err) { 3310ef82d3SMarcel Ziswiler debug("%s: Cannot find PMIC I2C chip\n", __func__); 3410ef82d3SMarcel Ziswiler return err; 3510ef82d3SMarcel Ziswiler } 3610ef82d3SMarcel Ziswiler 3710ef82d3SMarcel Ziswiler addr = PMU_SUPPLYENE; 3810ef82d3SMarcel Ziswiler 3910ef82d3SMarcel Ziswiler err = dm_i2c_read(dev, addr, data, 1); 4010ef82d3SMarcel Ziswiler if (err) { 4110ef82d3SMarcel Ziswiler debug("failed to get PMU_SUPPLYENE\n"); 4210ef82d3SMarcel Ziswiler return err; 4310ef82d3SMarcel Ziswiler } 4410ef82d3SMarcel Ziswiler 4510ef82d3SMarcel Ziswiler data[0] &= ~PMU_SUPPLYENE_SYSINEN; 4610ef82d3SMarcel Ziswiler data[0] |= PMU_SUPPLYENE_EXITSLREQ; 4710ef82d3SMarcel Ziswiler 4810ef82d3SMarcel Ziswiler err = dm_i2c_write(dev, addr, data, 1); 4910ef82d3SMarcel Ziswiler if (err) { 5010ef82d3SMarcel Ziswiler debug("failed to set PMU_SUPPLYENE\n"); 5110ef82d3SMarcel Ziswiler return err; 5210ef82d3SMarcel Ziswiler } 5310ef82d3SMarcel Ziswiler 54b7b20670SMarcel Ziswiler /* make sure SODIMM pin 87 nRESET_OUT is released properly */ 55b7b20670SMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI); 56b7b20670SMarcel Ziswiler 57a5825625SMarcel Ziswiler if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == 58a5825625SMarcel Ziswiler NVBOOTTYPE_RECOVERY) 59a5825625SMarcel Ziswiler printf("USB recovery mode\n"); 60a5825625SMarcel Ziswiler 61a5825625SMarcel Ziswiler return 0; 62a5825625SMarcel Ziswiler } 63e57c6e5bSMarcel Ziswiler 64e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_MMC 65e57c6e5bSMarcel Ziswiler /* 66e57c6e5bSMarcel Ziswiler * Routine: pin_mux_mmc 67e57c6e5bSMarcel Ziswiler * Description: setup the pin muxes/tristate values for the SDMMC(s) 68e57c6e5bSMarcel Ziswiler */ 69e57c6e5bSMarcel Ziswiler void pin_mux_mmc(void) 70e57c6e5bSMarcel Ziswiler { 71e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); 72e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GMB); 73e57c6e5bSMarcel Ziswiler } 74e57c6e5bSMarcel Ziswiler #endif 75e57c6e5bSMarcel Ziswiler 76e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_NAND 77e57c6e5bSMarcel Ziswiler void pin_mux_nand(void) 78e57c6e5bSMarcel Ziswiler { 79e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); 8076a30fedSMarcel Ziswiler 8176a30fedSMarcel Ziswiler /* 8276a30fedSMarcel Ziswiler * configure pingroup ATC to something unrelated to 8376a30fedSMarcel Ziswiler * avoid ATC overriding KBC 8476a30fedSMarcel Ziswiler */ 8576a30fedSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); 86e57c6e5bSMarcel Ziswiler } 87e57c6e5bSMarcel Ziswiler #endif 88e57c6e5bSMarcel Ziswiler 89e57c6e5bSMarcel Ziswiler #ifdef CONFIG_USB_EHCI_TEGRA 90e57c6e5bSMarcel Ziswiler void pin_mux_usb(void) 91e57c6e5bSMarcel Ziswiler { 92e57c6e5bSMarcel Ziswiler /* module internal USB bus to connect ethernet chipset */ 93e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); 94e57c6e5bSMarcel Ziswiler 95e57c6e5bSMarcel Ziswiler /* ULPI reference clock output */ 96e57c6e5bSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); 97e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_CDEV2); 98e57c6e5bSMarcel Ziswiler 99e57c6e5bSMarcel Ziswiler /* PHY reset GPIO */ 100e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_UAC); 101e57c6e5bSMarcel Ziswiler 102e57c6e5bSMarcel Ziswiler /* VBus GPIO */ 103e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_DTE); 104e57c6e5bSMarcel Ziswiler 10500a5270bSMarcel Ziswiler /* Reset ASIX using LAN_RESET */ 10600a5270bSMarcel Ziswiler gpio_request(GPIO_PV4, "LAN_RESET"); 10700a5270bSMarcel Ziswiler gpio_direction_output(GPIO_PV4, 0); 10800a5270bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GPV); 10900a5270bSMarcel Ziswiler udelay(5); 11000a5270bSMarcel Ziswiler gpio_set_value(GPIO_PV4, 1); 11100a5270bSMarcel Ziswiler 11200a5270bSMarcel Ziswiler /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ 113e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_SPIG); 114e57c6e5bSMarcel Ziswiler } 115e57c6e5bSMarcel Ziswiler #endif 116b2ea19b5SMarcel Ziswiler 117*d2f90650SSimon Glass #ifdef CONFIG_VIDEO_TEGRA20 118b2ea19b5SMarcel Ziswiler /* 119b2ea19b5SMarcel Ziswiler * Routine: pin_mux_display 120b2ea19b5SMarcel Ziswiler * Description: setup the pin muxes/tristate values for the LCD interface) 121b2ea19b5SMarcel Ziswiler */ 122b2ea19b5SMarcel Ziswiler void pin_mux_display(void) 123b2ea19b5SMarcel Ziswiler { 124b2ea19b5SMarcel Ziswiler /* 125b2ea19b5SMarcel Ziswiler * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through 126b2ea19b5SMarcel Ziswiler * device-tree 127b2ea19b5SMarcel Ziswiler */ 128b2ea19b5SMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_DTA); 129b2ea19b5SMarcel Ziswiler 130b2ea19b5SMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); 131b2ea19b5SMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_SDC); 132b2ea19b5SMarcel Ziswiler } 133b2ea19b5SMarcel Ziswiler #endif 134