1e57c6e5bSMarcel Ziswiler /* 2e57c6e5bSMarcel Ziswiler * Copyright (C) 2012 Lucas Stach 3e57c6e5bSMarcel Ziswiler * 4e57c6e5bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 5e57c6e5bSMarcel Ziswiler */ 6e57c6e5bSMarcel Ziswiler 7e57c6e5bSMarcel Ziswiler #include <common.h> 8e57c6e5bSMarcel Ziswiler #include <asm/arch/clock.h> 9e57c6e5bSMarcel Ziswiler #include <asm/arch/funcmux.h> 10e57c6e5bSMarcel Ziswiler #include <asm/arch/pinmux.h> 11a5825625SMarcel Ziswiler #include <asm/arch-tegra/ap.h> 12e57c6e5bSMarcel Ziswiler #include <asm/arch-tegra/board.h> 13a5825625SMarcel Ziswiler #include <asm/arch-tegra/tegra.h> 14e57c6e5bSMarcel Ziswiler #include <asm/gpio.h> 15a5825625SMarcel Ziswiler #include <asm/io.h> 1610ef82d3SMarcel Ziswiler #include <i2c.h> 17*b891d010SMarcel Ziswiler #include <nand.h> 18*b891d010SMarcel Ziswiler 19*b891d010SMarcel Ziswiler DECLARE_GLOBAL_DATA_PTR; 2010ef82d3SMarcel Ziswiler 2110ef82d3SMarcel Ziswiler #define PMU_I2C_ADDRESS 0x34 2210ef82d3SMarcel Ziswiler #define MAX_I2C_RETRY 3 2310ef82d3SMarcel Ziswiler #define PMU_SUPPLYENE 0x14 2410ef82d3SMarcel Ziswiler #define PMU_SUPPLYENE_SYSINEN (1<<5) 2510ef82d3SMarcel Ziswiler #define PMU_SUPPLYENE_EXITSLREQ (1<<1) 26a5825625SMarcel Ziswiler 27a5825625SMarcel Ziswiler int arch_misc_init(void) 28a5825625SMarcel Ziswiler { 2910ef82d3SMarcel Ziswiler /* Disable PMIC sleep mode on low supply voltage */ 3010ef82d3SMarcel Ziswiler struct udevice *dev; 3110ef82d3SMarcel Ziswiler u8 addr, data[1]; 3210ef82d3SMarcel Ziswiler int err; 3310ef82d3SMarcel Ziswiler 3410ef82d3SMarcel Ziswiler err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); 3510ef82d3SMarcel Ziswiler if (err) { 3610ef82d3SMarcel Ziswiler debug("%s: Cannot find PMIC I2C chip\n", __func__); 3710ef82d3SMarcel Ziswiler return err; 3810ef82d3SMarcel Ziswiler } 3910ef82d3SMarcel Ziswiler 4010ef82d3SMarcel Ziswiler addr = PMU_SUPPLYENE; 4110ef82d3SMarcel Ziswiler 4210ef82d3SMarcel Ziswiler err = dm_i2c_read(dev, addr, data, 1); 4310ef82d3SMarcel Ziswiler if (err) { 4410ef82d3SMarcel Ziswiler debug("failed to get PMU_SUPPLYENE\n"); 4510ef82d3SMarcel Ziswiler return err; 4610ef82d3SMarcel Ziswiler } 4710ef82d3SMarcel Ziswiler 4810ef82d3SMarcel Ziswiler data[0] &= ~PMU_SUPPLYENE_SYSINEN; 4910ef82d3SMarcel Ziswiler data[0] |= PMU_SUPPLYENE_EXITSLREQ; 5010ef82d3SMarcel Ziswiler 5110ef82d3SMarcel Ziswiler err = dm_i2c_write(dev, addr, data, 1); 5210ef82d3SMarcel Ziswiler if (err) { 5310ef82d3SMarcel Ziswiler debug("failed to set PMU_SUPPLYENE\n"); 5410ef82d3SMarcel Ziswiler return err; 5510ef82d3SMarcel Ziswiler } 5610ef82d3SMarcel Ziswiler 57b7b20670SMarcel Ziswiler /* make sure SODIMM pin 87 nRESET_OUT is released properly */ 58b7b20670SMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_ATA, PMUX_FUNC_GMI); 59b7b20670SMarcel Ziswiler 60a5825625SMarcel Ziswiler if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == 61a5825625SMarcel Ziswiler NVBOOTTYPE_RECOVERY) 62a5825625SMarcel Ziswiler printf("USB recovery mode\n"); 63a5825625SMarcel Ziswiler 64a5825625SMarcel Ziswiler return 0; 65a5825625SMarcel Ziswiler } 66e57c6e5bSMarcel Ziswiler 67*b891d010SMarcel Ziswiler int checkboard(void) 68*b891d010SMarcel Ziswiler { 69*b891d010SMarcel Ziswiler printf("Model: Toradex Colibri T20 %dMB V%s\n", 70*b891d010SMarcel Ziswiler (gd->ram_size == 0x10000000) ? 256 : 512, 71*b891d010SMarcel Ziswiler (nand_info[0]->erasesize >> 10 == 512) ? 72*b891d010SMarcel Ziswiler ((gd->ram_size == 0x10000000) ? "1.1B" : "1.1C") : "1.2A"); 73*b891d010SMarcel Ziswiler 74*b891d010SMarcel Ziswiler return 0; 75*b891d010SMarcel Ziswiler } 76*b891d010SMarcel Ziswiler 77e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_MMC 78e57c6e5bSMarcel Ziswiler /* 79e57c6e5bSMarcel Ziswiler * Routine: pin_mux_mmc 80e57c6e5bSMarcel Ziswiler * Description: setup the pin muxes/tristate values for the SDMMC(s) 81e57c6e5bSMarcel Ziswiler */ 82e57c6e5bSMarcel Ziswiler void pin_mux_mmc(void) 83e57c6e5bSMarcel Ziswiler { 84e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); 85e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GMB); 86e57c6e5bSMarcel Ziswiler } 87e57c6e5bSMarcel Ziswiler #endif 88e57c6e5bSMarcel Ziswiler 89e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_NAND 90e57c6e5bSMarcel Ziswiler void pin_mux_nand(void) 91e57c6e5bSMarcel Ziswiler { 92e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); 9376a30fedSMarcel Ziswiler 9476a30fedSMarcel Ziswiler /* 9576a30fedSMarcel Ziswiler * configure pingroup ATC to something unrelated to 9676a30fedSMarcel Ziswiler * avoid ATC overriding KBC 9776a30fedSMarcel Ziswiler */ 9876a30fedSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); 99e57c6e5bSMarcel Ziswiler } 100e57c6e5bSMarcel Ziswiler #endif 101e57c6e5bSMarcel Ziswiler 102e57c6e5bSMarcel Ziswiler #ifdef CONFIG_USB_EHCI_TEGRA 103e57c6e5bSMarcel Ziswiler void pin_mux_usb(void) 104e57c6e5bSMarcel Ziswiler { 105e57c6e5bSMarcel Ziswiler /* module internal USB bus to connect ethernet chipset */ 106e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); 107e57c6e5bSMarcel Ziswiler 108e57c6e5bSMarcel Ziswiler /* ULPI reference clock output */ 109e57c6e5bSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); 110e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_CDEV2); 111e57c6e5bSMarcel Ziswiler 112e57c6e5bSMarcel Ziswiler /* PHY reset GPIO */ 113e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_UAC); 114e57c6e5bSMarcel Ziswiler 115e57c6e5bSMarcel Ziswiler /* VBus GPIO */ 116e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_DTE); 117e57c6e5bSMarcel Ziswiler 11800a5270bSMarcel Ziswiler /* Reset ASIX using LAN_RESET */ 11901a97a11SStephen Warren gpio_request(TEGRA_GPIO(V, 4), "LAN_RESET"); 12001a97a11SStephen Warren gpio_direction_output(TEGRA_GPIO(V, 4), 0); 12100a5270bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GPV); 12200a5270bSMarcel Ziswiler udelay(5); 12301a97a11SStephen Warren gpio_set_value(TEGRA_GPIO(V, 4), 1); 12400a5270bSMarcel Ziswiler 12500a5270bSMarcel Ziswiler /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ 126e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_SPIG); 127e57c6e5bSMarcel Ziswiler } 128e57c6e5bSMarcel Ziswiler #endif 129b2ea19b5SMarcel Ziswiler 130d2f90650SSimon Glass #ifdef CONFIG_VIDEO_TEGRA20 131b2ea19b5SMarcel Ziswiler /* 132b2ea19b5SMarcel Ziswiler * Routine: pin_mux_display 133b2ea19b5SMarcel Ziswiler * Description: setup the pin muxes/tristate values for the LCD interface) 134b2ea19b5SMarcel Ziswiler */ 135b2ea19b5SMarcel Ziswiler void pin_mux_display(void) 136b2ea19b5SMarcel Ziswiler { 137b2ea19b5SMarcel Ziswiler /* 138b2ea19b5SMarcel Ziswiler * Manually untristate BL_ON (PT4 - SODIMM 71) as specified through 139b2ea19b5SMarcel Ziswiler * device-tree 140b2ea19b5SMarcel Ziswiler */ 141b2ea19b5SMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_DTA); 142b2ea19b5SMarcel Ziswiler 143b2ea19b5SMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_SDC, PMUX_FUNC_PWM); 144b2ea19b5SMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_SDC); 145b2ea19b5SMarcel Ziswiler } 146b2ea19b5SMarcel Ziswiler #endif 147