1e57c6e5bSMarcel Ziswiler /* 2e57c6e5bSMarcel Ziswiler * Copyright (C) 2012 Lucas Stach 3e57c6e5bSMarcel Ziswiler * 4e57c6e5bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 5e57c6e5bSMarcel Ziswiler */ 6e57c6e5bSMarcel Ziswiler 7e57c6e5bSMarcel Ziswiler #include <common.h> 8e57c6e5bSMarcel Ziswiler #include <asm/arch/clock.h> 9e57c6e5bSMarcel Ziswiler #include <asm/arch/funcmux.h> 10e57c6e5bSMarcel Ziswiler #include <asm/arch/pinmux.h> 11*a5825625SMarcel Ziswiler #include <asm/arch-tegra/ap.h> 12e57c6e5bSMarcel Ziswiler #include <asm/arch-tegra/board.h> 13*a5825625SMarcel Ziswiler #include <asm/arch-tegra/tegra.h> 14e57c6e5bSMarcel Ziswiler #include <asm/gpio.h> 15*a5825625SMarcel Ziswiler #include <asm/io.h> 16*a5825625SMarcel Ziswiler 17*a5825625SMarcel Ziswiler int arch_misc_init(void) 18*a5825625SMarcel Ziswiler { 19*a5825625SMarcel Ziswiler if (readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BOOTTYPE) == 20*a5825625SMarcel Ziswiler NVBOOTTYPE_RECOVERY) 21*a5825625SMarcel Ziswiler printf("USB recovery mode\n"); 22*a5825625SMarcel Ziswiler 23*a5825625SMarcel Ziswiler return 0; 24*a5825625SMarcel Ziswiler } 25e57c6e5bSMarcel Ziswiler 26e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_MMC 27e57c6e5bSMarcel Ziswiler /* 28e57c6e5bSMarcel Ziswiler * Routine: pin_mux_mmc 29e57c6e5bSMarcel Ziswiler * Description: setup the pin muxes/tristate values for the SDMMC(s) 30e57c6e5bSMarcel Ziswiler */ 31e57c6e5bSMarcel Ziswiler void pin_mux_mmc(void) 32e57c6e5bSMarcel Ziswiler { 33e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); 34e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GMB); 35e57c6e5bSMarcel Ziswiler } 36e57c6e5bSMarcel Ziswiler #endif 37e57c6e5bSMarcel Ziswiler 38e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_NAND 39e57c6e5bSMarcel Ziswiler void pin_mux_nand(void) 40e57c6e5bSMarcel Ziswiler { 41e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); 4276a30fedSMarcel Ziswiler 4376a30fedSMarcel Ziswiler /* 4476a30fedSMarcel Ziswiler * configure pingroup ATC to something unrelated to 4576a30fedSMarcel Ziswiler * avoid ATC overriding KBC 4676a30fedSMarcel Ziswiler */ 4776a30fedSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_ATC, PMUX_FUNC_GMI); 48e57c6e5bSMarcel Ziswiler } 49e57c6e5bSMarcel Ziswiler #endif 50e57c6e5bSMarcel Ziswiler 51e57c6e5bSMarcel Ziswiler #ifdef CONFIG_USB_EHCI_TEGRA 52e57c6e5bSMarcel Ziswiler void pin_mux_usb(void) 53e57c6e5bSMarcel Ziswiler { 54e57c6e5bSMarcel Ziswiler /* module internal USB bus to connect ethernet chipset */ 55e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); 56e57c6e5bSMarcel Ziswiler 57e57c6e5bSMarcel Ziswiler /* ULPI reference clock output */ 58e57c6e5bSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); 59e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_CDEV2); 60e57c6e5bSMarcel Ziswiler 61e57c6e5bSMarcel Ziswiler /* PHY reset GPIO */ 62e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_UAC); 63e57c6e5bSMarcel Ziswiler 64e57c6e5bSMarcel Ziswiler /* VBus GPIO */ 65e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_DTE); 66e57c6e5bSMarcel Ziswiler 6700a5270bSMarcel Ziswiler /* Reset ASIX using LAN_RESET */ 6800a5270bSMarcel Ziswiler gpio_request(GPIO_PV4, "LAN_RESET"); 6900a5270bSMarcel Ziswiler gpio_direction_output(GPIO_PV4, 0); 7000a5270bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GPV); 7100a5270bSMarcel Ziswiler udelay(5); 7200a5270bSMarcel Ziswiler gpio_set_value(GPIO_PV4, 1); 7300a5270bSMarcel Ziswiler 7400a5270bSMarcel Ziswiler /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ 75e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_SPIG); 76e57c6e5bSMarcel Ziswiler } 77e57c6e5bSMarcel Ziswiler #endif 78