1e57c6e5bSMarcel Ziswiler /* 2e57c6e5bSMarcel Ziswiler * Copyright (C) 2012 Lucas Stach 3e57c6e5bSMarcel Ziswiler * 4e57c6e5bSMarcel Ziswiler * SPDX-License-Identifier: GPL-2.0+ 5e57c6e5bSMarcel Ziswiler */ 6e57c6e5bSMarcel Ziswiler 7e57c6e5bSMarcel Ziswiler #include <common.h> 8e57c6e5bSMarcel Ziswiler #include <asm/arch/clock.h> 9e57c6e5bSMarcel Ziswiler #include <asm/arch/funcmux.h> 10e57c6e5bSMarcel Ziswiler #include <asm/arch/pinmux.h> 11e57c6e5bSMarcel Ziswiler #include <asm/arch-tegra/board.h> 12e57c6e5bSMarcel Ziswiler #include <asm/gpio.h> 13e57c6e5bSMarcel Ziswiler 14e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_MMC 15e57c6e5bSMarcel Ziswiler /* 16e57c6e5bSMarcel Ziswiler * Routine: pin_mux_mmc 17e57c6e5bSMarcel Ziswiler * Description: setup the pin muxes/tristate values for the SDMMC(s) 18e57c6e5bSMarcel Ziswiler */ 19e57c6e5bSMarcel Ziswiler void pin_mux_mmc(void) 20e57c6e5bSMarcel Ziswiler { 21e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_SDMMC4, FUNCMUX_SDMMC4_ATB_GMA_4_BIT); 22e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GMB); 23e57c6e5bSMarcel Ziswiler } 24e57c6e5bSMarcel Ziswiler #endif 25e57c6e5bSMarcel Ziswiler 26e57c6e5bSMarcel Ziswiler #ifdef CONFIG_TEGRA_NAND 27e57c6e5bSMarcel Ziswiler void pin_mux_nand(void) 28e57c6e5bSMarcel Ziswiler { 29e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_NDFLASH_KBC_8_BIT); 30e57c6e5bSMarcel Ziswiler } 31e57c6e5bSMarcel Ziswiler #endif 32e57c6e5bSMarcel Ziswiler 33e57c6e5bSMarcel Ziswiler #ifdef CONFIG_USB_EHCI_TEGRA 34e57c6e5bSMarcel Ziswiler void pin_mux_usb(void) 35e57c6e5bSMarcel Ziswiler { 36e57c6e5bSMarcel Ziswiler /* module internal USB bus to connect ethernet chipset */ 37e57c6e5bSMarcel Ziswiler funcmux_select(PERIPH_ID_USB2, FUNCMUX_USB2_ULPI); 38e57c6e5bSMarcel Ziswiler 39e57c6e5bSMarcel Ziswiler /* ULPI reference clock output */ 40e57c6e5bSMarcel Ziswiler pinmux_set_func(PMUX_PINGRP_CDEV2, PMUX_FUNC_PLLP_OUT4); 41e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_CDEV2); 42e57c6e5bSMarcel Ziswiler 43e57c6e5bSMarcel Ziswiler /* PHY reset GPIO */ 44e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_UAC); 45e57c6e5bSMarcel Ziswiler 46e57c6e5bSMarcel Ziswiler /* VBus GPIO */ 47e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_DTE); 48e57c6e5bSMarcel Ziswiler 49*00a5270bSMarcel Ziswiler /* Reset ASIX using LAN_RESET */ 50*00a5270bSMarcel Ziswiler gpio_request(GPIO_PV4, "LAN_RESET"); 51*00a5270bSMarcel Ziswiler gpio_direction_output(GPIO_PV4, 0); 52*00a5270bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_GPV); 53*00a5270bSMarcel Ziswiler udelay(5); 54*00a5270bSMarcel Ziswiler gpio_set_value(GPIO_PV4, 1); 55*00a5270bSMarcel Ziswiler 56*00a5270bSMarcel Ziswiler /* USBH_PEN: USB 1 aka Tegra USB port 3 VBus */ 57e57c6e5bSMarcel Ziswiler pinmux_tristate_disable(PMUX_PINGRP_SPIG); 58e57c6e5bSMarcel Ziswiler } 59e57c6e5bSMarcel Ziswiler #endif 60