1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Toradex Colibri PXA270 Support
4  *
5  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
6  * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
7  */
8 
9 #include <common.h>
10 #include <dm.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/pxa.h>
13 #include <asm/arch/regs-mmc.h>
14 #include <asm/arch/regs-uart.h>
15 #include <asm/io.h>
16 #include <dm/platdata.h>
17 #include <dm/platform_data/serial_pxa.h>
18 #include <netdev.h>
19 #include <serial.h>
20 #include <usb.h>
21 #include <asm/mach-types.h>
22 #include "../common/tdx-common.h"
23 
24 DECLARE_GLOBAL_DATA_PTR;
25 
26 int board_init(void)
27 {
28 	/* We have RAM, disable cache */
29 	dcache_disable();
30 	icache_disable();
31 
32 	/* arch number of Toradex Colibri PXA270 */
33 	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
34 
35 	/* adress of boot parameters */
36 	gd->bd->bi_boot_params = 0xa0000100;
37 
38 	return 0;
39 }
40 
41 int checkboard(void)
42 {
43 	puts("Model: Toradex Colibri PXA270\n");
44 
45 	return 0;
46 }
47 
48 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
49 int ft_board_setup(void *blob, bd_t *bd)
50 {
51 	return ft_common_board_setup(blob, bd);
52 }
53 #endif
54 
55 int dram_init(void)
56 {
57 	pxa2xx_dram_init();
58 	gd->ram_size = PHYS_SDRAM_1_SIZE;
59 	return 0;
60 }
61 
62 #ifdef	CONFIG_CMD_USB
63 int board_usb_init(int index, enum usb_init_type init)
64 {
65 	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
66 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
67 		UHCHR);
68 
69 	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
70 
71 	while (UHCHR & UHCHR_FSBIR)
72 		;
73 
74 	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
75 	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
76 
77 	/* Clear any OTG Pin Hold */
78 	if (readl(PSSR) & PSSR_OTGPH)
79 		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
80 
81 	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
82 	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
83 
84 	/* Set port power control mask bits, only 3 ports. */
85 	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
86 
87 	/* enable port 2 */
88 	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
89 		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
90 
91 	return 0;
92 }
93 
94 int board_usb_cleanup(int index, enum usb_init_type init)
95 {
96 	return 0;
97 }
98 
99 void usb_board_stop(void)
100 {
101 	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
102 	udelay(11);
103 	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
104 
105 	writel(readl(UHCCOMS) | 1, UHCCOMS);
106 	udelay(10);
107 
108 	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
109 
110 	return;
111 }
112 #endif
113 
114 #ifdef CONFIG_DRIVER_DM9000
115 int board_eth_init(bd_t *bis)
116 {
117 	return dm9000_initialize(bis);
118 }
119 #endif
120 
121 #ifdef	CONFIG_CMD_MMC
122 int board_mmc_init(bd_t *bis)
123 {
124 	pxa_mmc_register(0);
125 	return 0;
126 }
127 #endif
128 
129 static const struct pxa_serial_platdata serial_platdata = {
130 	.base = (struct pxa_uart_regs *)FFUART_BASE,
131 	.port = FFUART_INDEX,
132 	.baudrate = CONFIG_BAUDRATE,
133 };
134 
135 U_BOOT_DEVICE(pxa_serials) = {
136 	.name = "serial_pxa",
137 	.platdata = &serial_platdata,
138 };
139