1 /* 2 * Toradex Colibri PXA270 Support 3 * 4 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com> 5 * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10 #include <common.h> 11 #include <asm/arch/hardware.h> 12 #include <asm/arch/pxa.h> 13 #include <asm/arch/regs-mmc.h> 14 #include <asm/arch/regs-uart.h> 15 #include <asm/io.h> 16 #include <dm/platdata.h> 17 #include <dm/platform_data/serial_pxa.h> 18 #include <netdev.h> 19 #include <serial.h> 20 #include <usb.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 int board_init(void) 25 { 26 /* We have RAM, disable cache */ 27 dcache_disable(); 28 icache_disable(); 29 30 /* arch number of Toradex Colibri PXA270 */ 31 gd->bd->bi_arch_number = MACH_TYPE_COLIBRI; 32 33 /* adress of boot parameters */ 34 gd->bd->bi_boot_params = 0xa0000100; 35 36 return 0; 37 } 38 39 int checkboard(void) 40 { 41 puts("Model: Toradex Colibri PXA270\n"); 42 43 return 0; 44 } 45 46 int dram_init(void) 47 { 48 pxa2xx_dram_init(); 49 gd->ram_size = PHYS_SDRAM_1_SIZE; 50 return 0; 51 } 52 53 #ifdef CONFIG_CMD_USB 54 int board_usb_init(int index, enum usb_init_type init) 55 { 56 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & 57 ~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE), 58 UHCHR); 59 60 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); 61 62 while (UHCHR & UHCHR_FSBIR) 63 ; 64 65 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); 66 writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE); 67 68 /* Clear any OTG Pin Hold */ 69 if (readl(PSSR) & PSSR_OTGPH) 70 writel(readl(PSSR) | PSSR_OTGPH, PSSR); 71 72 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); 73 writel(readl(UHCRHDA) | 0x100, UHCRHDA); 74 75 /* Set port power control mask bits, only 3 ports. */ 76 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); 77 78 /* enable port 2 */ 79 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | 80 UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR); 81 82 return 0; 83 } 84 85 int board_usb_cleanup(int index, enum usb_init_type init) 86 { 87 return 0; 88 } 89 90 void usb_board_stop(void) 91 { 92 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); 93 udelay(11); 94 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); 95 96 writel(readl(UHCCOMS) | 1, UHCCOMS); 97 udelay(10); 98 99 writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN); 100 101 return; 102 } 103 #endif 104 105 #ifdef CONFIG_DRIVER_DM9000 106 int board_eth_init(bd_t *bis) 107 { 108 return dm9000_initialize(bis); 109 } 110 #endif 111 112 #ifdef CONFIG_CMD_MMC 113 int board_mmc_init(bd_t *bis) 114 { 115 pxa_mmc_register(0); 116 return 0; 117 } 118 #endif 119 120 static const struct pxa_serial_platdata serial_platdata = { 121 .base = (struct pxa_uart_regs *)FFUART_BASE, 122 .port = FFUART_INDEX, 123 .baudrate = CONFIG_BAUDRATE, 124 }; 125 126 U_BOOT_DEVICE(pxa_serials) = { 127 .name = "serial_pxa", 128 .platdata = &serial_platdata, 129 }; 130