1 /*
2  * Toradex Colibri PXA270 Support
3  *
4  * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
5  * Copyright (C) 2016 Marcel Ziswiler <marcel.ziswiler@toradex.com>
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <asm/arch/hardware.h>
12 #include <asm/arch/pxa.h>
13 #include <asm/arch/regs-mmc.h>
14 #include <asm/arch/regs-uart.h>
15 #include <asm/io.h>
16 #include <dm/platdata.h>
17 #include <dm/platform_data/serial_pxa.h>
18 #include <netdev.h>
19 #include <serial.h>
20 #include <usb.h>
21 #include "../common/tdx-common.h"
22 
23 DECLARE_GLOBAL_DATA_PTR;
24 
25 int board_init(void)
26 {
27 	/* We have RAM, disable cache */
28 	dcache_disable();
29 	icache_disable();
30 
31 	/* arch number of Toradex Colibri PXA270 */
32 	gd->bd->bi_arch_number = MACH_TYPE_COLIBRI;
33 
34 	/* adress of boot parameters */
35 	gd->bd->bi_boot_params = 0xa0000100;
36 
37 	return 0;
38 }
39 
40 int checkboard(void)
41 {
42 	puts("Model: Toradex Colibri PXA270\n");
43 
44 	return 0;
45 }
46 
47 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
48 int ft_board_setup(void *blob, bd_t *bd)
49 {
50 	return ft_common_board_setup(blob, bd);
51 }
52 #endif
53 
54 int dram_init(void)
55 {
56 	pxa2xx_dram_init();
57 	gd->ram_size = PHYS_SDRAM_1_SIZE;
58 	return 0;
59 }
60 
61 #ifdef	CONFIG_CMD_USB
62 int board_usb_init(int index, enum usb_init_type init)
63 {
64 	writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) &
65 		~(UHCHR_SSEP0 | UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSE),
66 		UHCHR);
67 
68 	writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR);
69 
70 	while (UHCHR & UHCHR_FSBIR)
71 		;
72 
73 	writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR);
74 	writel((UHCHIE_UPRIE | UHCHIE_RWIE), UHCHIE);
75 
76 	/* Clear any OTG Pin Hold */
77 	if (readl(PSSR) & PSSR_OTGPH)
78 		writel(readl(PSSR) | PSSR_OTGPH, PSSR);
79 
80 	writel(readl(UHCRHDA) & ~(0x200), UHCRHDA);
81 	writel(readl(UHCRHDA) | 0x100, UHCRHDA);
82 
83 	/* Set port power control mask bits, only 3 ports. */
84 	writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB);
85 
86 	/* enable port 2 */
87 	writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS |
88 		UP2OCR_DMPDE | UP2OCR_DPPDE, UP2OCR);
89 
90 	return 0;
91 }
92 
93 int board_usb_cleanup(int index, enum usb_init_type init)
94 {
95 	return 0;
96 }
97 
98 void usb_board_stop(void)
99 {
100 	writel(readl(UHCHR) | UHCHR_FHR, UHCHR);
101 	udelay(11);
102 	writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR);
103 
104 	writel(readl(UHCCOMS) | 1, UHCCOMS);
105 	udelay(10);
106 
107 	writel(readl(CKEN) & ~CKEN10_USBHOST, CKEN);
108 
109 	return;
110 }
111 #endif
112 
113 #ifdef CONFIG_DRIVER_DM9000
114 int board_eth_init(bd_t *bis)
115 {
116 	return dm9000_initialize(bis);
117 }
118 #endif
119 
120 #ifdef	CONFIG_CMD_MMC
121 int board_mmc_init(bd_t *bis)
122 {
123 	pxa_mmc_register(0);
124 	return 0;
125 }
126 #endif
127 
128 static const struct pxa_serial_platdata serial_platdata = {
129 	.base = (struct pxa_uart_regs *)FFUART_BASE,
130 	.port = FFUART_INDEX,
131 	.baudrate = CONFIG_BAUDRATE,
132 };
133 
134 U_BOOT_DEVICE(pxa_serials) = {
135 	.name = "serial_pxa",
136 	.platdata = &serial_platdata,
137 };
138