1/*
2 * Copyright (C) 2015 Freescale Semiconductor, Inc.
3 *               2015 Toradex AG
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 *
7 * Refer docs/README.imxmage for more details about how-to configure
8 * and create imximage boot image
9 *
10 * The syntax is taken as close as possible with the kwbimage
11 */
12
13#define __ASSEMBLY__
14#include <config.h>
15
16/* image version */
17
18IMAGE_VERSION 2
19
20/*
21 * Boot Device : sd
22 */
23
24BOOT_FROM	sd
25
26/*
27 * Secure boot support
28 */
29#ifdef CONFIG_SECURE_BOOT
30CSF CONFIG_CSF_SIZE
31#endif
32
33/*
34 * Device Configuration Data (DCD)
35 *
36 * Each entry must have the format:
37 * Addr-type           Address        Value
38 *
39 * where:
40 *	Addr-type register length (1,2 or 4 bytes)
41 *	Address	  absolute address of the register
42 *	value	  value to be stored in the register
43 */
44
45/* IOMUXC_GPR_GPR1 */
46DATA 4 0x30340004 0x4F400005
47
48/* DDR3L */
49/* assuming MEMC_FREQ_RATIO = 2 */
50/* SRC_DDRC_RCR */
51DATA 4 0x30391000 0x00000002
52/* DDRC_MSTR */
53DATA 4 0x307a0000 0x01040001
54/* DDRC_DFIUPD0 */
55DATA 4 0x307a01a0 0x80400003
56/* DDRC_DFIUPD1 */
57DATA 4 0x307a01a4 0x00100020
58/* DDRC_DFIUPD2 */
59DATA 4 0x307a01a8 0x80100004
60/* DDRC_RFSHTMG */
61DATA 4 0x307a0064 0x00400045
62/* DDRC_MP_PCTRL_0 */
63DATA 4 0x307a0490 0x00000001
64/* DDRC_INIT0 */
65DATA 4 0x307a00d0 0x00020083
66/* DDRC_INIT1 */
67DATA 4 0x307a00d4 0x00690000
68/* DDRC_INIT3 MR0/MR1 */
69DATA 4 0x307a00dc 0x09300004
70/* DDRC_INIT4 MR2/MR3 */
71DATA 4 0x307a00e0 0x04480000
72/* DDRC_INIT5 */
73DATA 4 0x307a00e4 0x00100004
74/* DDRC_RANKCTL */
75DATA 4 0x307a00f4 0x0000033f
76/* DDRC_DRAMTMG0 */
77DATA 4 0x307a0100 0x090b090a
78/* DDRC_DRAMTMG1 */
79DATA 4 0x307a0104 0x000d020d
80/* DDRC_DRAMTMG2 */
81DATA 4 0x307a0108 0x03040307
82/* DDRC_DRAMTMG3 */
83DATA 4 0x307a010c 0x00002006
84/* DDRC_DRAMTMG4 */
85DATA 4 0x307a0110 0x04020205
86/* DDRC_DRAMTMG5 */
87DATA 4 0x307a0114 0x03030202
88/* DDRC_DRAMTMG8 */
89DATA 4 0x307a0120 0x00000803
90/* DDRC_ZQCTL0 */
91DATA 4 0x307a0180 0x00800020
92/* DDRC_ZQCTL1 */
93DATA 4 0x307a0184 0x02001000
94/* DDRC_DFITMG0 */
95DATA 4 0x307a0190 0x02098204
96/* DDRC_DFITMG1 */
97DATA 4 0x307a0194 0x00030303
98/* DDRC_ADDRMAP0 */
99DATA 4 0x307a0200 0x0000001f
100/* DDRC_ADDRMAP1 */
101DATA 4 0x307a0204 0x00080808
102/* DDRC_ADDRMAP5 */
103DATA 4 0x307a0214 0x07070707
104/* DDRC_ADDRMAP6 */
105DATA 4 0x307a0218 0x07070707
106/* DDRC_ODTCFG */
107DATA 4 0x307a0240 0x06000601
108/* DDRC_ODTMAP */
109DATA 4 0x307a0244 0x00000011
110/* SRC_DDRC_RCR */
111DATA 4 0x30391000 0x00000000
112/* DDR_PHY_PHY_CON0 */
113DATA 4 0x30790000 0x17420f40
114/* DDR_PHY_PHY_CON1 */
115DATA 4 0x30790004 0x10210100
116/* DDR_PHY_PHY_CON4 */
117DATA 4 0x30790010 0x00060807
118/* DDR_PHY_MDLL_CON0 */
119DATA 4 0x307900b0 0x1010007e
120/* DDR_PHY_DRVDS_CON0 */
121DATA 4 0x3079009c 0x00000d6e
122/* DDR_PHY_OFFSET_RD_CON0 */
123DATA 4 0x30790020 0x08080808
124/* DDR_PHY_OFFSET_WR_CON0 */
125DATA 4 0x30790030 0x08080808
126/* DDR_PHY_CMD_SDLL_CON0 */
127DATA 4 0x30790050 0x01000010
128DATA 4 0x30790050 0x00000010
129
130/* DDR_PHY_ZQ_CON0 */
131DATA 4 0x307900c0 0x0e407304
132DATA 4 0x307900c0 0x0e447304
133DATA 4 0x307900c0 0x0e447306
134/* DDR_PHY_ZQ_CON1 */
135CHECK_BITS_SET 4 0x307900c4 0x1
136/* DDR_PHY_ZQ_CON0 */
137DATA 4 0x307900c0 0x0e447304
138DATA 4 0x307900c0 0x0e407304
139
140/* CCM_CCGRn */
141DATA 4 0x30384130 0x00000000
142/* IOMUXC_GPR_GPR8 */
143DATA 4 0x30340020 0x00000178
144/* CCM_CCGRn */
145DATA 4 0x30384130 0x00000002
146/* DDR_PHY_LP_CON0 */
147DATA 4 0x30790018 0x0000000f
148
149/* DDRC_STAT */
150CHECK_BITS_SET 4 0x307a0004 0x1
151