1 /* 2 * Copyright (C) 2016 Toradex AG 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <asm/arch/clock.h> 8 #include <asm/arch/crm_regs.h> 9 #include <asm/arch/imx-regs.h> 10 #include <asm/arch/mx7-pins.h> 11 #include <asm/arch/sys_proto.h> 12 #include <asm/gpio.h> 13 #include <asm/imx-common/boot_mode.h> 14 #include <asm/imx-common/iomux-v3.h> 15 #include <asm/io.h> 16 #include <common.h> 17 #include <dm.h> 18 #include <dm/platform_data/serial_mxc.h> 19 #include <fsl_esdhc.h> 20 #include <linux/sizes.h> 21 #include <mmc.h> 22 #include <miiphy.h> 23 #include <netdev.h> 24 #include <power/pmic.h> 25 #include <power/rn5t567_pmic.h> 26 #include <usb/ehci-ci.h> 27 #include "../common/tdx-common.h" 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 32 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 33 34 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 35 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 36 37 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 38 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 39 40 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 41 42 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 43 PAD_CTL_DSE_3P3V_49OHM) 44 45 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 46 47 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 48 49 int dram_init(void) 50 { 51 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 52 53 return 0; 54 } 55 56 static iomux_v3_cfg_t const uart1_pads[] = { 57 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 58 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 59 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 60 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 61 }; 62 63 static iomux_v3_cfg_t const usdhc1_pads[] = { 64 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 71 MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), 72 }; 73 74 #ifdef CONFIG_NAND_MXS 75 static iomux_v3_cfg_t const gpmi_pads[] = { 76 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 77 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 78 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 79 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 80 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 81 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 82 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 83 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 84 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 85 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 86 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 87 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 88 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 89 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 90 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 91 }; 92 93 static void setup_gpmi_nand(void) 94 { 95 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 96 97 /* NAND_USDHC_BUS_CLK is set in rom */ 98 set_clk_nand(); 99 } 100 #endif 101 102 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 103 MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104 MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105 MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106 MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107 MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108 MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109 MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110 MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 111 MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112 MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113 MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114 115 MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116 }; 117 118 #ifdef CONFIG_VIDEO_MXS 119 static iomux_v3_cfg_t const lcd_pads[] = { 120 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 121 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 122 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 123 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 124 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 125 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 126 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 127 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 128 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 129 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 130 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 131 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 132 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 133 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 137 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 138 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 139 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 140 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 141 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 142 }; 143 144 static iomux_v3_cfg_t const backlight_pads[] = { 145 /* Backlight On */ 146 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 147 /* Backlight PWM<A> (multiplexed pin) */ 148 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), 149 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 150 }; 151 152 #define GPIO_BL_ON IMX_GPIO_NR(5, 1) 153 #define GPIO_PWM_A IMX_GPIO_NR(1, 8) 154 155 static int setup_lcd(void) 156 { 157 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 158 159 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); 160 161 /* Set BL_ON */ 162 gpio_request(GPIO_BL_ON, "BL_ON"); 163 gpio_direction_output(GPIO_BL_ON, 1); 164 165 /* Set PWM<A> to full brightness (assuming inversed polarity) */ 166 gpio_request(GPIO_PWM_A, "PWM<A>"); 167 gpio_direction_output(GPIO_PWM_A, 0); 168 169 return 0; 170 } 171 #endif 172 173 #ifdef CONFIG_FEC_MXC 174 static iomux_v3_cfg_t const fec1_pads[] = { 175 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 176 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, 177 #else 178 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 179 #endif 180 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 181 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 182 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 183 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 184 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 185 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 186 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 187 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 188 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 189 }; 190 191 static void setup_iomux_fec(void) 192 { 193 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 194 } 195 #endif 196 197 static void setup_iomux_uart(void) 198 { 199 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 200 } 201 202 #ifdef CONFIG_FSL_ESDHC 203 204 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) 205 206 static struct fsl_esdhc_cfg usdhc_cfg[] = { 207 {USDHC1_BASE_ADDR, 0, 4}, 208 }; 209 210 int board_mmc_getcd(struct mmc *mmc) 211 { 212 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 213 int ret = 0; 214 215 switch (cfg->esdhc_base) { 216 case USDHC1_BASE_ADDR: 217 ret = !gpio_get_value(USDHC1_CD_GPIO); 218 break; 219 } 220 221 return ret; 222 } 223 224 int board_mmc_init(bd_t *bis) 225 { 226 int i, ret; 227 /* USDHC1 is mmc0 */ 228 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 229 switch (i) { 230 case 0: 231 imx_iomux_v3_setup_multiple_pads( 232 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 233 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 234 gpio_direction_input(USDHC1_CD_GPIO); 235 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 236 break; 237 default: 238 printf("Warning: you configured more USDHC controllers" 239 "(%d) than supported by the board\n", i + 1); 240 return -EINVAL; 241 } 242 243 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 244 if (ret) 245 return ret; 246 } 247 248 return 0; 249 } 250 #endif 251 252 #ifdef CONFIG_FEC_MXC 253 int board_eth_init(bd_t *bis) 254 { 255 int ret; 256 257 setup_iomux_fec(); 258 259 ret = fecmxc_initialize_multi(bis, 0, 260 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 261 if (ret) 262 printf("FEC1 MXC: %s:failed\n", __func__); 263 264 return ret; 265 } 266 267 static int setup_fec(void) 268 { 269 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 270 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 271 272 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 273 /* 274 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] 275 * and output it on the pin 276 */ 277 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 278 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 279 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); 280 #else 281 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ 282 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 283 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 284 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); 285 #endif 286 287 return set_clk_enet(ENET_50MHz); 288 } 289 290 int board_phy_config(struct phy_device *phydev) 291 { 292 if (phydev->drv->config) 293 phydev->drv->config(phydev); 294 return 0; 295 } 296 #endif 297 298 int board_early_init_f(void) 299 { 300 setup_iomux_uart(); 301 302 return 0; 303 } 304 305 int board_init(void) 306 { 307 /* address of boot parameters */ 308 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 309 310 #ifdef CONFIG_FEC_MXC 311 setup_fec(); 312 #endif 313 314 #ifdef CONFIG_NAND_MXS 315 setup_gpmi_nand(); 316 #endif 317 318 #ifdef CONFIG_VIDEO_MXS 319 setup_lcd(); 320 #endif 321 322 return 0; 323 } 324 325 #ifdef CONFIG_CMD_BMODE 326 static const struct boot_mode board_boot_modes[] = { 327 /* 4 bit bus width */ 328 {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, 329 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 330 {NULL, 0}, 331 }; 332 #endif 333 334 int board_late_init(void) 335 { 336 #ifdef CONFIG_CMD_BMODE 337 add_board_boot_modes(board_boot_modes); 338 #endif 339 340 return 0; 341 } 342 343 #ifdef CONFIG_DM_PMIC 344 int power_init_board(void) 345 { 346 struct udevice *dev; 347 int reg, ver; 348 int ret; 349 350 351 ret = pmic_get("rn5t567", &dev); 352 if (ret) 353 return ret; 354 ver = pmic_reg_read(dev, RN5T567_LSIVER); 355 reg = pmic_reg_read(dev, RN5T567_OTPVER); 356 357 printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); 358 359 /* set judge and press timer of N_OE to minimal values */ 360 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); 361 362 return 0; 363 } 364 365 void reset_cpu(ulong addr) 366 { 367 struct udevice *dev; 368 369 pmic_get("rn5t567", &dev); 370 371 /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ 372 pmic_reg_write(dev, RN5T567_REPCNT, 0x1); 373 pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); 374 375 /* 376 * Re-power factor detection on PMIC side is not instant. 1ms 377 * proved to be enough time until reset takes effect. 378 */ 379 mdelay(1); 380 } 381 #endif 382 383 int checkboard(void) 384 { 385 printf("Model: Toradex Colibri iMX7%c\n", 386 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); 387 388 return 0; 389 } 390 391 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 392 int ft_board_setup(void *blob, bd_t *bd) 393 { 394 return ft_common_board_setup(blob, bd); 395 } 396 #endif 397 398 #ifdef CONFIG_USB_EHCI_MX7 399 static iomux_v3_cfg_t const usb_otg2_pads[] = { 400 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 401 }; 402 403 int board_ehci_hcd_init(int port) 404 { 405 switch (port) { 406 case 0: 407 break; 408 case 1: 409 if (is_cpu_type(MXC_CPU_MX7S)) 410 return -ENODEV; 411 412 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 413 ARRAY_SIZE(usb_otg2_pads)); 414 break; 415 default: 416 return -EINVAL; 417 } 418 return 0; 419 } 420 #endif 421