1 /*
2  * Copyright (C) 2016 Toradex AG
3  *
4  * SPDX-License-Identifier:	GPL-2.0+
5  */
6 
7 #include <asm/arch/clock.h>
8 #include <asm/arch/crm_regs.h>
9 #include <asm/arch/imx-regs.h>
10 #include <asm/arch/mx7-pins.h>
11 #include <asm/arch/sys_proto.h>
12 #include <asm/gpio.h>
13 #include <asm/imx-common/boot_mode.h>
14 #include <asm/imx-common/iomux-v3.h>
15 #include <asm/io.h>
16 #include <common.h>
17 #include <dm.h>
18 #include <dm/platform_data/serial_mxc.h>
19 #include <fdt_support.h>
20 #include <fsl_esdhc.h>
21 #include <jffs2/load_kernel.h>
22 #include <linux/sizes.h>
23 #include <mmc.h>
24 #include <miiphy.h>
25 #include <mtd_node.h>
26 #include <netdev.h>
27 #include <power/pmic.h>
28 #include <power/rn5t567_pmic.h>
29 #include <usb.h>
30 #include <usb/ehci-ci.h>
31 #include "../common/tdx-common.h"
32 
33 DECLARE_GLOBAL_DATA_PTR;
34 
35 #define UART_PAD_CTRL  (PAD_CTL_DSE_3P3V_49OHM | \
36 	PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS)
37 
38 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \
39 	PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
40 
41 #define ENET_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
42 #define ENET_PAD_CTRL_MII  (PAD_CTL_DSE_3P3V_32OHM)
43 
44 #define ENET_RX_PAD_CTRL  (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM)
45 
46 #define LCD_PAD_CTRL    (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \
47 	PAD_CTL_DSE_3P3V_49OHM)
48 
49 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
50 
51 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
52 
53 #define USB_CDET_GPIO	IMX_GPIO_NR(7, 14)
54 
55 int dram_init(void)
56 {
57 	gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
58 
59 	return 0;
60 }
61 
62 static iomux_v3_cfg_t const uart1_pads[] = {
63 	MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
64 	MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
65 	MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL),
66 	MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL),
67 };
68 
69 static iomux_v3_cfg_t const usdhc1_pads[] = {
70 	MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
71 	MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
72 	MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
73 	MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
74 	MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 	MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 
77 	MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL),
78 };
79 
80 #ifdef CONFIG_USB_EHCI_MX7
81 static iomux_v3_cfg_t const usb_cdet_pads[] = {
82 	MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL),
83 };
84 #endif
85 
86 #ifdef CONFIG_NAND_MXS
87 static iomux_v3_cfg_t const gpmi_pads[] = {
88 	MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
89 	MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
90 	MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
91 	MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
92 	MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
93 	MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
94 	MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
95 	MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
96 	MX7D_PAD_SD3_CLK__NAND_CLE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
97 	MX7D_PAD_SD3_CMD__NAND_ALE	| MUX_PAD_CTRL(NAND_PAD_CTRL),
98 	MX7D_PAD_SD3_STROBE__NAND_RE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
99 	MX7D_PAD_SD3_RESET_B__NAND_WE_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
100 	MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
101 	MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B	| MUX_PAD_CTRL(NAND_PAD_CTRL),
102 	MX7D_PAD_SAI1_TX_DATA__NAND_READY_B	| MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
103 };
104 
105 static void setup_gpmi_nand(void)
106 {
107 	imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
108 
109 	/* NAND_USDHC_BUS_CLK is set in rom */
110 	set_clk_nand();
111 }
112 #endif
113 
114 static iomux_v3_cfg_t const usdhc3_emmc_pads[] = {
115 	MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 	MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 	MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118 	MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
119 	MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
120 	MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
121 	MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
122 	MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
123 	MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
124 	MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
125 	MX7D_PAD_SD3_STROBE__SD3_STROBE	 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
126 
127 	MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
128 };
129 
130 #ifdef CONFIG_VIDEO_MXS
131 static iomux_v3_cfg_t const lcd_pads[] = {
132 	MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
133 	MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL),
134 	MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
135 	MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL),
136 	MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL),
137 	MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL),
138 	MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL),
139 	MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL),
140 	MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL),
141 	MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL),
142 	MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL),
143 	MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL),
144 	MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL),
145 	MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL),
146 	MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
147 	MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
148 	MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
149 	MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
150 	MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
151 	MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
152 	MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
153 	MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
154 };
155 
156 static iomux_v3_cfg_t const backlight_pads[] = {
157 	/* Backlight On */
158 	MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL),
159 	/* Backlight PWM<A> (multiplexed pin) */
160 	MX7D_PAD_GPIO1_IO08__GPIO1_IO8   | MUX_PAD_CTRL(NO_PAD_CTRL),
161 	MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL),
162 };
163 
164 #define GPIO_BL_ON IMX_GPIO_NR(5, 1)
165 #define GPIO_PWM_A IMX_GPIO_NR(1, 8)
166 
167 static int setup_lcd(void)
168 {
169 	imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads));
170 
171 	imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads));
172 
173 	/* Set BL_ON */
174 	gpio_request(GPIO_BL_ON, "BL_ON");
175 	gpio_direction_output(GPIO_BL_ON, 1);
176 
177 	/* Set PWM<A> to full brightness (assuming inversed polarity) */
178 	gpio_request(GPIO_PWM_A, "PWM<A>");
179 	gpio_direction_output(GPIO_PWM_A, 0);
180 
181 	return 0;
182 }
183 #endif
184 
185 #ifdef CONFIG_FEC_MXC
186 static iomux_v3_cfg_t const fec1_pads[] = {
187 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
188 	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION,
189 #else
190 	MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
191 #endif
192 	MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
193 	MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII),
194 	MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
195 	MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
196 	MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
197 	MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL	  | MUX_PAD_CTRL(ENET_RX_PAD_CTRL),
198 	MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
199 	MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
200 	MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),
201 };
202 
203 static void setup_iomux_fec(void)
204 {
205 	imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
206 }
207 #endif
208 
209 static void setup_iomux_uart(void)
210 {
211 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
212 }
213 
214 #ifdef CONFIG_FSL_ESDHC
215 
216 #define USDHC1_CD_GPIO	IMX_GPIO_NR(1, 0)
217 
218 static struct fsl_esdhc_cfg usdhc_cfg[] = {
219 	{USDHC1_BASE_ADDR, 0, 4},
220 };
221 
222 int board_mmc_getcd(struct mmc *mmc)
223 {
224 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
225 	int ret = 0;
226 
227 	switch (cfg->esdhc_base) {
228 	case USDHC1_BASE_ADDR:
229 		ret = !gpio_get_value(USDHC1_CD_GPIO);
230 		break;
231 	}
232 
233 	return ret;
234 }
235 
236 int board_mmc_init(bd_t *bis)
237 {
238 	int i, ret;
239 	/* USDHC1 is mmc0 */
240 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
241 		switch (i) {
242 		case 0:
243 			imx_iomux_v3_setup_multiple_pads(
244 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
245 			gpio_request(USDHC1_CD_GPIO, "usdhc1_cd");
246 			gpio_direction_input(USDHC1_CD_GPIO);
247 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
248 			break;
249 		default:
250 			printf("Warning: you configured more USDHC controllers"
251 				"(%d) than supported by the board\n", i + 1);
252 			return -EINVAL;
253 		}
254 
255 		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
256 		if (ret)
257 			return ret;
258 	}
259 
260 	return 0;
261 }
262 #endif
263 
264 #ifdef CONFIG_FEC_MXC
265 int board_eth_init(bd_t *bis)
266 {
267 	int ret;
268 
269 	setup_iomux_fec();
270 
271 	ret = fecmxc_initialize_multi(bis, 0,
272 		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
273 	if (ret)
274 		printf("FEC1 MXC: %s:failed\n", __func__);
275 
276 	return ret;
277 }
278 
279 static int setup_fec(void)
280 {
281 	struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
282 		= (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
283 
284 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK
285 	/*
286 	 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17]
287 	 * and output it on the pin
288 	 */
289 	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
290 			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK,
291 			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK);
292 #else
293 	/* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */
294 	clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
295 			IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK,
296 			IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK);
297 #endif
298 
299 	return set_clk_enet(ENET_50MHz);
300 }
301 
302 int board_phy_config(struct phy_device *phydev)
303 {
304 	if (phydev->drv->config)
305 		phydev->drv->config(phydev);
306 	return 0;
307 }
308 #endif
309 
310 int board_early_init_f(void)
311 {
312 	setup_iomux_uart();
313 
314 	return 0;
315 }
316 
317 int board_init(void)
318 {
319 	/* address of boot parameters */
320 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
321 
322 #ifdef CONFIG_FEC_MXC
323 	setup_fec();
324 #endif
325 
326 #ifdef CONFIG_NAND_MXS
327 	setup_gpmi_nand();
328 #endif
329 
330 #ifdef CONFIG_VIDEO_MXS
331 	setup_lcd();
332 #endif
333 
334 #ifdef CONFIG_USB_EHCI_MX7
335 	imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads));
336 	gpio_request(USB_CDET_GPIO, "usb-cdet-gpio");
337 #endif
338 
339 	return 0;
340 }
341 
342 #ifdef CONFIG_CMD_BMODE
343 static const struct boot_mode board_boot_modes[] = {
344 	/* 4 bit bus width */
345 	{"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)},
346 	{"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)},
347 	{NULL, 0},
348 };
349 #endif
350 
351 int board_late_init(void)
352 {
353 #ifdef CONFIG_CMD_BMODE
354 	add_board_boot_modes(board_boot_modes);
355 #endif
356 
357 	return 0;
358 }
359 
360 #ifdef CONFIG_DM_PMIC
361 int power_init_board(void)
362 {
363 	struct udevice *dev;
364 	int reg, ver;
365 	int ret;
366 
367 
368 	ret = pmic_get("rn5t567", &dev);
369 	if (ret)
370 		return ret;
371 	ver = pmic_reg_read(dev, RN5T567_LSIVER);
372 	reg = pmic_reg_read(dev, RN5T567_OTPVER);
373 
374 	printf("PMIC:  RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg);
375 
376 	/* set judge and press timer of N_OE to minimal values */
377 	pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0);
378 
379 	/* configure sleep slot for 3.3V Ethernet */
380 	reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT);
381 	reg = (reg & 0xf0) | reg >> 4;
382 	pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg);
383 
384 	/* disable DCDC2 discharge to avoid backfeeding through VFB2 */
385 	pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0);
386 
387 	/* configure sleep slot for ARM rail */
388 	reg = pmic_reg_read(dev, RN5T567_DC2_SLOT);
389 	reg = (reg & 0xf0) | reg >> 4;
390 	pmic_reg_write(dev, RN5T567_DC2_SLOT, reg);
391 
392 	/* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */
393 	pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0);
394 
395 	return 0;
396 }
397 
398 void reset_cpu(ulong addr)
399 {
400 	struct udevice *dev;
401 
402 	pmic_get("rn5t567", &dev);
403 
404 	/* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */
405 	pmic_reg_write(dev, RN5T567_REPCNT, 0x1);
406 	pmic_reg_write(dev, RN5T567_SLPCNT, 0x1);
407 
408 	/*
409 	 * Re-power factor detection on PMIC side is not instant. 1ms
410 	 * proved to be enough time until reset takes effect.
411 	 */
412 	mdelay(1);
413 }
414 #endif
415 
416 int checkboard(void)
417 {
418 	printf("Model: Toradex Colibri iMX7%c\n",
419 	       is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S');
420 
421 	return 0;
422 }
423 
424 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
425 int ft_board_setup(void *blob, bd_t *bd)
426 {
427 #if defined(CONFIG_FDT_FIXUP_PARTITIONS)
428 	static struct node_info nodes[] = {
429 		{ "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */
430 	};
431 
432 	/* Update partition nodes using info from mtdparts env var */
433 	puts("   Updating MTD partitions...\n");
434 	fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
435 #endif
436 
437 	return ft_common_board_setup(blob, bd);
438 }
439 #endif
440 
441 #ifdef CONFIG_USB_EHCI_MX7
442 static iomux_v3_cfg_t const usb_otg2_pads[] = {
443 	MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
444 };
445 
446 int board_ehci_hcd_init(int port)
447 {
448 	switch (port) {
449 	case 0:
450 		break;
451 	case 1:
452 		if (is_cpu_type(MXC_CPU_MX7S))
453 			return -ENODEV;
454 
455 		imx_iomux_v3_setup_multiple_pads(usb_otg2_pads,
456 						 ARRAY_SIZE(usb_otg2_pads));
457 		break;
458 	default:
459 		return -EINVAL;
460 	}
461 	return 0;
462 }
463 
464 int board_usb_phy_mode(int port)
465 {
466 	switch (port) {
467 	case 0:
468 		if (gpio_get_value(USB_CDET_GPIO))
469 			return USB_INIT_DEVICE;
470 		else
471 			return USB_INIT_HOST;
472 	case 1:
473 	default:
474 		return USB_INIT_HOST;
475 	}
476 }
477 #endif
478