1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2016 Toradex AG 4 */ 5 6 #include <asm/arch/clock.h> 7 #include <asm/arch/crm_regs.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch/mx7-pins.h> 10 #include <asm/arch/sys_proto.h> 11 #include <asm/gpio.h> 12 #include <asm/mach-imx/iomux-v3.h> 13 #include <asm/io.h> 14 #include <common.h> 15 #include <dm.h> 16 #include <dm/platform_data/serial_mxc.h> 17 #include <fdt_support.h> 18 #include <fsl_esdhc.h> 19 #include <jffs2/load_kernel.h> 20 #include <linux/sizes.h> 21 #include <mmc.h> 22 #include <miiphy.h> 23 #include <mtd_node.h> 24 #include <netdev.h> 25 #include <power/pmic.h> 26 #include <power/rn5t567_pmic.h> 27 #include <usb.h> 28 #include <usb/ehci-ci.h> 29 #include "../common/tdx-common.h" 30 31 DECLARE_GLOBAL_DATA_PTR; 32 33 #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 34 PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 35 36 #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 37 PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 38 39 #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 40 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 41 42 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 43 44 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 45 PAD_CTL_DSE_3P3V_49OHM) 46 47 #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 48 49 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 50 51 #define USB_CDET_GPIO IMX_GPIO_NR(7, 14) 52 53 int dram_init(void) 54 { 55 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 56 57 return 0; 58 } 59 60 static iomux_v3_cfg_t const uart1_pads[] = { 61 MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 62 MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 63 MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 64 MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 65 }; 66 67 static iomux_v3_cfg_t const usdhc1_pads[] = { 68 MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69 MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70 MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71 MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72 MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73 MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74 75 MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), 76 }; 77 78 #ifdef CONFIG_USB_EHCI_MX7 79 static iomux_v3_cfg_t const usb_cdet_pads[] = { 80 MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 81 }; 82 #endif 83 84 #ifdef CONFIG_NAND_MXS 85 static iomux_v3_cfg_t const gpmi_pads[] = { 86 MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 87 MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 88 MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 89 MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 90 MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 91 MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 92 MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 93 MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 94 MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 95 MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 96 MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 97 MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 98 MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 99 MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 100 MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 101 }; 102 103 static void setup_gpmi_nand(void) 104 { 105 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 106 107 /* NAND_USDHC_BUS_CLK is set in rom */ 108 set_clk_nand(); 109 } 110 #endif 111 112 #ifdef CONFIG_VIDEO_MXS 113 static iomux_v3_cfg_t const lcd_pads[] = { 114 MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 115 MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 116 MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 117 MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 118 MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 119 MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 120 MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 121 MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 122 MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 123 MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 124 MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 125 MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 126 MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 127 MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 128 MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 129 MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 130 MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 131 MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 132 MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 133 MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134 MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135 MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136 }; 137 138 static iomux_v3_cfg_t const backlight_pads[] = { 139 /* Backlight On */ 140 MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 141 /* Backlight PWM<A> (multiplexed pin) */ 142 MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), 143 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 144 }; 145 146 #define GPIO_BL_ON IMX_GPIO_NR(5, 1) 147 #define GPIO_PWM_A IMX_GPIO_NR(1, 8) 148 149 static int setup_lcd(void) 150 { 151 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 152 153 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); 154 155 /* Set BL_ON */ 156 gpio_request(GPIO_BL_ON, "BL_ON"); 157 gpio_direction_output(GPIO_BL_ON, 1); 158 159 /* Set PWM<A> to full brightness (assuming inversed polarity) */ 160 gpio_request(GPIO_PWM_A, "PWM<A>"); 161 gpio_direction_output(GPIO_PWM_A, 0); 162 163 return 0; 164 } 165 #endif 166 167 #ifdef CONFIG_FEC_MXC 168 static iomux_v3_cfg_t const fec1_pads[] = { 169 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 170 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, 171 #else 172 MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 173 #endif 174 MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 175 MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 176 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 177 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 178 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 179 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 180 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 181 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 182 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 183 }; 184 185 static void setup_iomux_fec(void) 186 { 187 imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 188 } 189 #endif 190 191 static void setup_iomux_uart(void) 192 { 193 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 194 } 195 196 #ifdef CONFIG_FSL_ESDHC 197 198 #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) 199 200 static struct fsl_esdhc_cfg usdhc_cfg[] = { 201 {USDHC1_BASE_ADDR, 0, 4}, 202 }; 203 204 int board_mmc_getcd(struct mmc *mmc) 205 { 206 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 207 int ret = 0; 208 209 switch (cfg->esdhc_base) { 210 case USDHC1_BASE_ADDR: 211 ret = !gpio_get_value(USDHC1_CD_GPIO); 212 break; 213 } 214 215 return ret; 216 } 217 218 int board_mmc_init(bd_t *bis) 219 { 220 int i, ret; 221 /* USDHC1 is mmc0 */ 222 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 223 switch (i) { 224 case 0: 225 imx_iomux_v3_setup_multiple_pads( 226 usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 227 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 228 gpio_direction_input(USDHC1_CD_GPIO); 229 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 230 break; 231 default: 232 printf("Warning: you configured more USDHC controllers" 233 "(%d) than supported by the board\n", i + 1); 234 return -EINVAL; 235 } 236 237 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 238 if (ret) 239 return ret; 240 } 241 242 return 0; 243 } 244 #endif 245 246 #ifdef CONFIG_FEC_MXC 247 int board_eth_init(bd_t *bis) 248 { 249 int ret; 250 251 setup_iomux_fec(); 252 253 ret = fecmxc_initialize_multi(bis, 0, 254 CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 255 if (ret) 256 printf("FEC1 MXC: %s:failed\n", __func__); 257 258 return ret; 259 } 260 261 static int setup_fec(void) 262 { 263 struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 264 = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 265 266 #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 267 /* 268 * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] 269 * and output it on the pin 270 */ 271 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 272 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 273 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); 274 #else 275 /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ 276 clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 277 IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 278 IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); 279 #endif 280 281 return set_clk_enet(ENET_50MHZ); 282 } 283 284 int board_phy_config(struct phy_device *phydev) 285 { 286 if (phydev->drv->config) 287 phydev->drv->config(phydev); 288 return 0; 289 } 290 #endif 291 292 int board_early_init_f(void) 293 { 294 setup_iomux_uart(); 295 296 return 0; 297 } 298 299 int board_init(void) 300 { 301 /* address of boot parameters */ 302 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 303 304 #ifdef CONFIG_FEC_MXC 305 setup_fec(); 306 #endif 307 308 #ifdef CONFIG_NAND_MXS 309 setup_gpmi_nand(); 310 #endif 311 312 #ifdef CONFIG_VIDEO_MXS 313 setup_lcd(); 314 #endif 315 316 #ifdef CONFIG_USB_EHCI_MX7 317 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); 318 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); 319 #endif 320 321 return 0; 322 } 323 324 #ifdef CONFIG_DM_PMIC 325 int power_init_board(void) 326 { 327 struct udevice *dev; 328 int reg, ver; 329 int ret; 330 331 332 ret = pmic_get("rn5t567", &dev); 333 if (ret) 334 return ret; 335 ver = pmic_reg_read(dev, RN5T567_LSIVER); 336 reg = pmic_reg_read(dev, RN5T567_OTPVER); 337 338 printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); 339 340 /* set judge and press timer of N_OE to minimal values */ 341 pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); 342 343 /* configure sleep slot for 3.3V Ethernet */ 344 reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT); 345 reg = (reg & 0xf0) | reg >> 4; 346 pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg); 347 348 /* disable DCDC2 discharge to avoid backfeeding through VFB2 */ 349 pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); 350 351 /* configure sleep slot for ARM rail */ 352 reg = pmic_reg_read(dev, RN5T567_DC2_SLOT); 353 reg = (reg & 0xf0) | reg >> 4; 354 pmic_reg_write(dev, RN5T567_DC2_SLOT, reg); 355 356 /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */ 357 pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); 358 359 return 0; 360 } 361 362 void reset_cpu(ulong addr) 363 { 364 struct udevice *dev; 365 366 pmic_get("rn5t567", &dev); 367 368 /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ 369 pmic_reg_write(dev, RN5T567_REPCNT, 0x1); 370 pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); 371 372 /* 373 * Re-power factor detection on PMIC side is not instant. 1ms 374 * proved to be enough time until reset takes effect. 375 */ 376 mdelay(1); 377 } 378 #endif 379 380 int checkboard(void) 381 { 382 printf("Model: Toradex Colibri iMX7%c\n", 383 is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); 384 385 return 0; 386 } 387 388 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 389 int ft_board_setup(void *blob, bd_t *bd) 390 { 391 #if defined(CONFIG_FDT_FIXUP_PARTITIONS) 392 static const struct node_info nodes[] = { 393 { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 394 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, 395 }; 396 397 /* Update partition nodes using info from mtdparts env var */ 398 puts(" Updating MTD partitions...\n"); 399 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 400 #endif 401 402 return ft_common_board_setup(blob, bd); 403 } 404 #endif 405 406 #ifdef CONFIG_USB_EHCI_MX7 407 static iomux_v3_cfg_t const usb_otg2_pads[] = { 408 MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 409 }; 410 411 int board_ehci_hcd_init(int port) 412 { 413 switch (port) { 414 case 0: 415 break; 416 case 1: 417 if (is_cpu_type(MXC_CPU_MX7S)) 418 return -ENODEV; 419 420 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 421 ARRAY_SIZE(usb_otg2_pads)); 422 break; 423 default: 424 return -EINVAL; 425 } 426 return 0; 427 } 428 429 int board_usb_phy_mode(int port) 430 { 431 switch (port) { 432 case 0: 433 if (gpio_get_value(USB_CDET_GPIO)) 434 return USB_INIT_DEVICE; 435 else 436 return USB_INIT_HOST; 437 case 1: 438 default: 439 return USB_INIT_HOST; 440 } 441 } 442 #endif 443