183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2ae440ab0SStefan Agner /* 3ae440ab0SStefan Agner * Copyright (C) 2016 Toradex AG 4ae440ab0SStefan Agner */ 5ae440ab0SStefan Agner 6ae440ab0SStefan Agner #include <asm/arch/clock.h> 7ae440ab0SStefan Agner #include <asm/arch/crm_regs.h> 8ae440ab0SStefan Agner #include <asm/arch/imx-regs.h> 9ae440ab0SStefan Agner #include <asm/arch/mx7-pins.h> 10ae440ab0SStefan Agner #include <asm/arch/sys_proto.h> 11ae440ab0SStefan Agner #include <asm/gpio.h> 12552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 13ae440ab0SStefan Agner #include <asm/io.h> 14ae440ab0SStefan Agner #include <common.h> 15ae440ab0SStefan Agner #include <dm.h> 16ae440ab0SStefan Agner #include <dm/platform_data/serial_mxc.h> 1764095704SStefan Agner #include <fdt_support.h> 18ae440ab0SStefan Agner #include <fsl_esdhc.h> 1964095704SStefan Agner #include <jffs2/load_kernel.h> 20ae440ab0SStefan Agner #include <linux/sizes.h> 21ae440ab0SStefan Agner #include <mmc.h> 22ae440ab0SStefan Agner #include <miiphy.h> 2364095704SStefan Agner #include <mtd_node.h> 24ae440ab0SStefan Agner #include <netdev.h> 2502ad90ecSStefan Agner #include <power/pmic.h> 2602ad90ecSStefan Agner #include <power/rn5t567_pmic.h> 275a986dfeSStefan Agner #include <usb.h> 28ae440ab0SStefan Agner #include <usb/ehci-ci.h> 2937fa4125SStefan Agner #include "../common/tdx-common.h" 30ae440ab0SStefan Agner 31ae440ab0SStefan Agner DECLARE_GLOBAL_DATA_PTR; 32ae440ab0SStefan Agner 33ae440ab0SStefan Agner #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 34ae440ab0SStefan Agner PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 35ae440ab0SStefan Agner 36ae440ab0SStefan Agner #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 37ae440ab0SStefan Agner PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 38ae440ab0SStefan Agner 39ae440ab0SStefan Agner #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 40ae440ab0SStefan Agner #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 41ae440ab0SStefan Agner 42ae440ab0SStefan Agner #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 43ae440ab0SStefan Agner 44ae440ab0SStefan Agner #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 45ae440ab0SStefan Agner PAD_CTL_DSE_3P3V_49OHM) 46ae440ab0SStefan Agner 47ae440ab0SStefan Agner #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 48ae440ab0SStefan Agner 49ae440ab0SStefan Agner #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 50ae440ab0SStefan Agner 515a986dfeSStefan Agner #define USB_CDET_GPIO IMX_GPIO_NR(7, 14) 525a986dfeSStefan Agner 53ae440ab0SStefan Agner int dram_init(void) 54ae440ab0SStefan Agner { 55ae440ab0SStefan Agner gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 56ae440ab0SStefan Agner 57ae440ab0SStefan Agner return 0; 58ae440ab0SStefan Agner } 59ae440ab0SStefan Agner 60ae440ab0SStefan Agner static iomux_v3_cfg_t const uart1_pads[] = { 61ae440ab0SStefan Agner MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 62ae440ab0SStefan Agner MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 63ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 64ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 65ae440ab0SStefan Agner }; 66ae440ab0SStefan Agner 67ae440ab0SStefan Agner static iomux_v3_cfg_t const usdhc1_pads[] = { 68ae440ab0SStefan Agner MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69ae440ab0SStefan Agner MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70ae440ab0SStefan Agner MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71ae440ab0SStefan Agner MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72ae440ab0SStefan Agner MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73ae440ab0SStefan Agner MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 74ae440ab0SStefan Agner 75ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), 76ae440ab0SStefan Agner }; 77ae440ab0SStefan Agner 785a986dfeSStefan Agner #ifdef CONFIG_USB_EHCI_MX7 795a986dfeSStefan Agner static iomux_v3_cfg_t const usb_cdet_pads[] = { 805a986dfeSStefan Agner MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 815a986dfeSStefan Agner }; 825a986dfeSStefan Agner #endif 835a986dfeSStefan Agner 84ae440ab0SStefan Agner #ifdef CONFIG_NAND_MXS 85ae440ab0SStefan Agner static iomux_v3_cfg_t const gpmi_pads[] = { 86ae440ab0SStefan Agner MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 87ae440ab0SStefan Agner MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 88ae440ab0SStefan Agner MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 89ae440ab0SStefan Agner MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 90ae440ab0SStefan Agner MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 91ae440ab0SStefan Agner MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 92ae440ab0SStefan Agner MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 93ae440ab0SStefan Agner MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 94ae440ab0SStefan Agner MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 95ae440ab0SStefan Agner MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 96ae440ab0SStefan Agner MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 97ae440ab0SStefan Agner MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 98ae440ab0SStefan Agner MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 99ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 100ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 101ae440ab0SStefan Agner }; 102ae440ab0SStefan Agner 103ae440ab0SStefan Agner static void setup_gpmi_nand(void) 104ae440ab0SStefan Agner { 105ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 106ae440ab0SStefan Agner 107ae440ab0SStefan Agner /* NAND_USDHC_BUS_CLK is set in rom */ 108ae440ab0SStefan Agner set_clk_nand(); 109ae440ab0SStefan Agner } 110ae440ab0SStefan Agner #endif 111ae440ab0SStefan Agner 112ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 113ae440ab0SStefan Agner static iomux_v3_cfg_t const lcd_pads[] = { 114ae440ab0SStefan Agner MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 115ae440ab0SStefan Agner MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 116ae440ab0SStefan Agner MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 117ae440ab0SStefan Agner MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 118ae440ab0SStefan Agner MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 119ae440ab0SStefan Agner MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 120ae440ab0SStefan Agner MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 121ae440ab0SStefan Agner MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 122ae440ab0SStefan Agner MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 123ae440ab0SStefan Agner MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 124ae440ab0SStefan Agner MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 125ae440ab0SStefan Agner MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 126ae440ab0SStefan Agner MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 127ae440ab0SStefan Agner MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 128ae440ab0SStefan Agner MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 129ae440ab0SStefan Agner MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 130ae440ab0SStefan Agner MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 131ae440ab0SStefan Agner MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 132ae440ab0SStefan Agner MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 133ae440ab0SStefan Agner MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134ae440ab0SStefan Agner MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135ae440ab0SStefan Agner MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136ae440ab0SStefan Agner }; 137ae440ab0SStefan Agner 138ae440ab0SStefan Agner static iomux_v3_cfg_t const backlight_pads[] = { 139ae440ab0SStefan Agner /* Backlight On */ 140ae440ab0SStefan Agner MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 141ae440ab0SStefan Agner /* Backlight PWM<A> (multiplexed pin) */ 142ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), 143ae440ab0SStefan Agner MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 144ae440ab0SStefan Agner }; 145ae440ab0SStefan Agner 146ae440ab0SStefan Agner #define GPIO_BL_ON IMX_GPIO_NR(5, 1) 147ae440ab0SStefan Agner #define GPIO_PWM_A IMX_GPIO_NR(1, 8) 148ae440ab0SStefan Agner 149ae440ab0SStefan Agner static int setup_lcd(void) 150ae440ab0SStefan Agner { 151ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 152ae440ab0SStefan Agner 153ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); 154ae440ab0SStefan Agner 155ae440ab0SStefan Agner /* Set BL_ON */ 156ae440ab0SStefan Agner gpio_request(GPIO_BL_ON, "BL_ON"); 157ae440ab0SStefan Agner gpio_direction_output(GPIO_BL_ON, 1); 158ae440ab0SStefan Agner 159ae440ab0SStefan Agner /* Set PWM<A> to full brightness (assuming inversed polarity) */ 160ae440ab0SStefan Agner gpio_request(GPIO_PWM_A, "PWM<A>"); 161ae440ab0SStefan Agner gpio_direction_output(GPIO_PWM_A, 0); 162ae440ab0SStefan Agner 163ae440ab0SStefan Agner return 0; 164ae440ab0SStefan Agner } 165ae440ab0SStefan Agner #endif 166ae440ab0SStefan Agner 167ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 168ae440ab0SStefan Agner static iomux_v3_cfg_t const fec1_pads[] = { 169ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 170ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, 171ae440ab0SStefan Agner #else 172ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 173ae440ab0SStefan Agner #endif 174ae440ab0SStefan Agner MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 175ae440ab0SStefan Agner MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 176ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 177ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 178ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 179ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 180ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 181ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 182ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 183ae440ab0SStefan Agner }; 184ae440ab0SStefan Agner 185ae440ab0SStefan Agner static void setup_iomux_fec(void) 186ae440ab0SStefan Agner { 187ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 188ae440ab0SStefan Agner } 189ae440ab0SStefan Agner #endif 190ae440ab0SStefan Agner 191ae440ab0SStefan Agner static void setup_iomux_uart(void) 192ae440ab0SStefan Agner { 193ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 194ae440ab0SStefan Agner } 195ae440ab0SStefan Agner 196ae440ab0SStefan Agner #ifdef CONFIG_FSL_ESDHC 197ae440ab0SStefan Agner 198ae440ab0SStefan Agner #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) 199ae440ab0SStefan Agner 200ae440ab0SStefan Agner static struct fsl_esdhc_cfg usdhc_cfg[] = { 201ae440ab0SStefan Agner {USDHC1_BASE_ADDR, 0, 4}, 202ae440ab0SStefan Agner }; 203ae440ab0SStefan Agner 204ae440ab0SStefan Agner int board_mmc_getcd(struct mmc *mmc) 205ae440ab0SStefan Agner { 206ae440ab0SStefan Agner struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 207ae440ab0SStefan Agner int ret = 0; 208ae440ab0SStefan Agner 209ae440ab0SStefan Agner switch (cfg->esdhc_base) { 210ae440ab0SStefan Agner case USDHC1_BASE_ADDR: 211ae440ab0SStefan Agner ret = !gpio_get_value(USDHC1_CD_GPIO); 212ae440ab0SStefan Agner break; 213ae440ab0SStefan Agner } 214ae440ab0SStefan Agner 215ae440ab0SStefan Agner return ret; 216ae440ab0SStefan Agner } 217ae440ab0SStefan Agner 218ae440ab0SStefan Agner int board_mmc_init(bd_t *bis) 219ae440ab0SStefan Agner { 220ae440ab0SStefan Agner int i, ret; 221ae440ab0SStefan Agner /* USDHC1 is mmc0 */ 222ae440ab0SStefan Agner for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 223ae440ab0SStefan Agner switch (i) { 224ae440ab0SStefan Agner case 0: 225ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads( 226ae440ab0SStefan Agner usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 227ae440ab0SStefan Agner gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 228ae440ab0SStefan Agner gpio_direction_input(USDHC1_CD_GPIO); 229ae440ab0SStefan Agner usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 230ae440ab0SStefan Agner break; 231ae440ab0SStefan Agner default: 232ae440ab0SStefan Agner printf("Warning: you configured more USDHC controllers" 233ae440ab0SStefan Agner "(%d) than supported by the board\n", i + 1); 234ae440ab0SStefan Agner return -EINVAL; 235ae440ab0SStefan Agner } 236ae440ab0SStefan Agner 237ae440ab0SStefan Agner ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 238ae440ab0SStefan Agner if (ret) 239ae440ab0SStefan Agner return ret; 240ae440ab0SStefan Agner } 241ae440ab0SStefan Agner 242ae440ab0SStefan Agner return 0; 243ae440ab0SStefan Agner } 244ae440ab0SStefan Agner #endif 245ae440ab0SStefan Agner 246ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 247ae440ab0SStefan Agner int board_eth_init(bd_t *bis) 248ae440ab0SStefan Agner { 249ae440ab0SStefan Agner int ret; 250ae440ab0SStefan Agner 251ae440ab0SStefan Agner setup_iomux_fec(); 252ae440ab0SStefan Agner 253ae440ab0SStefan Agner ret = fecmxc_initialize_multi(bis, 0, 254ae440ab0SStefan Agner CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 255ae440ab0SStefan Agner if (ret) 256ae440ab0SStefan Agner printf("FEC1 MXC: %s:failed\n", __func__); 257ae440ab0SStefan Agner 258ae440ab0SStefan Agner return ret; 259ae440ab0SStefan Agner } 260ae440ab0SStefan Agner 261ae440ab0SStefan Agner static int setup_fec(void) 262ae440ab0SStefan Agner { 263ae440ab0SStefan Agner struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 264ae440ab0SStefan Agner = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 265ae440ab0SStefan Agner 266ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 267ae440ab0SStefan Agner /* 268ae440ab0SStefan Agner * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] 269ae440ab0SStefan Agner * and output it on the pin 270ae440ab0SStefan Agner */ 271ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 272ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 273ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); 274ae440ab0SStefan Agner #else 275ae440ab0SStefan Agner /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ 276ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 277ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 278ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); 279ae440ab0SStefan Agner #endif 280ae440ab0SStefan Agner 2818590786aSEric Nelson return set_clk_enet(ENET_50MHZ); 282ae440ab0SStefan Agner } 283ae440ab0SStefan Agner 284ae440ab0SStefan Agner int board_phy_config(struct phy_device *phydev) 285ae440ab0SStefan Agner { 286ae440ab0SStefan Agner if (phydev->drv->config) 287ae440ab0SStefan Agner phydev->drv->config(phydev); 288ae440ab0SStefan Agner return 0; 289ae440ab0SStefan Agner } 290ae440ab0SStefan Agner #endif 291ae440ab0SStefan Agner 292ae440ab0SStefan Agner int board_early_init_f(void) 293ae440ab0SStefan Agner { 294ae440ab0SStefan Agner setup_iomux_uart(); 295ae440ab0SStefan Agner 296ae440ab0SStefan Agner return 0; 297ae440ab0SStefan Agner } 298ae440ab0SStefan Agner 299ae440ab0SStefan Agner int board_init(void) 300ae440ab0SStefan Agner { 301ae440ab0SStefan Agner /* address of boot parameters */ 302ae440ab0SStefan Agner gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 303ae440ab0SStefan Agner 304ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 305ae440ab0SStefan Agner setup_fec(); 306ae440ab0SStefan Agner #endif 307ae440ab0SStefan Agner 308ae440ab0SStefan Agner #ifdef CONFIG_NAND_MXS 309ae440ab0SStefan Agner setup_gpmi_nand(); 310ae440ab0SStefan Agner #endif 311ae440ab0SStefan Agner 312ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 313ae440ab0SStefan Agner setup_lcd(); 314ae440ab0SStefan Agner #endif 315ae440ab0SStefan Agner 3165a986dfeSStefan Agner #ifdef CONFIG_USB_EHCI_MX7 3175a986dfeSStefan Agner imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); 3185a986dfeSStefan Agner gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); 3195a986dfeSStefan Agner #endif 3205a986dfeSStefan Agner 321ae440ab0SStefan Agner return 0; 322ae440ab0SStefan Agner } 323ae440ab0SStefan Agner 32402ad90ecSStefan Agner #ifdef CONFIG_DM_PMIC 32502ad90ecSStefan Agner int power_init_board(void) 32602ad90ecSStefan Agner { 32702ad90ecSStefan Agner struct udevice *dev; 32802ad90ecSStefan Agner int reg, ver; 32902ad90ecSStefan Agner int ret; 33002ad90ecSStefan Agner 33102ad90ecSStefan Agner 33202ad90ecSStefan Agner ret = pmic_get("rn5t567", &dev); 33302ad90ecSStefan Agner if (ret) 33402ad90ecSStefan Agner return ret; 33502ad90ecSStefan Agner ver = pmic_reg_read(dev, RN5T567_LSIVER); 33602ad90ecSStefan Agner reg = pmic_reg_read(dev, RN5T567_OTPVER); 33702ad90ecSStefan Agner 33802ad90ecSStefan Agner printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); 33902ad90ecSStefan Agner 34002ad90ecSStefan Agner /* set judge and press timer of N_OE to minimal values */ 34102ad90ecSStefan Agner pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); 34202ad90ecSStefan Agner 34305ed964dSStefan Agner /* configure sleep slot for 3.3V Ethernet */ 34405ed964dSStefan Agner reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT); 34505ed964dSStefan Agner reg = (reg & 0xf0) | reg >> 4; 34605ed964dSStefan Agner pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg); 34705ed964dSStefan Agner 34805ed964dSStefan Agner /* disable DCDC2 discharge to avoid backfeeding through VFB2 */ 34905ed964dSStefan Agner pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); 35005ed964dSStefan Agner 35105ed964dSStefan Agner /* configure sleep slot for ARM rail */ 35205ed964dSStefan Agner reg = pmic_reg_read(dev, RN5T567_DC2_SLOT); 35305ed964dSStefan Agner reg = (reg & 0xf0) | reg >> 4; 35405ed964dSStefan Agner pmic_reg_write(dev, RN5T567_DC2_SLOT, reg); 35505ed964dSStefan Agner 35605ed964dSStefan Agner /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */ 35705ed964dSStefan Agner pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); 35805ed964dSStefan Agner 35902ad90ecSStefan Agner return 0; 36002ad90ecSStefan Agner } 36102ad90ecSStefan Agner 36202ad90ecSStefan Agner void reset_cpu(ulong addr) 36302ad90ecSStefan Agner { 36402ad90ecSStefan Agner struct udevice *dev; 36502ad90ecSStefan Agner 36602ad90ecSStefan Agner pmic_get("rn5t567", &dev); 36702ad90ecSStefan Agner 36802ad90ecSStefan Agner /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ 36902ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_REPCNT, 0x1); 37002ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); 37102ad90ecSStefan Agner 37202ad90ecSStefan Agner /* 37302ad90ecSStefan Agner * Re-power factor detection on PMIC side is not instant. 1ms 37402ad90ecSStefan Agner * proved to be enough time until reset takes effect. 37502ad90ecSStefan Agner */ 37602ad90ecSStefan Agner mdelay(1); 37702ad90ecSStefan Agner } 37802ad90ecSStefan Agner #endif 37902ad90ecSStefan Agner 380ae440ab0SStefan Agner int checkboard(void) 381ae440ab0SStefan Agner { 382ae440ab0SStefan Agner printf("Model: Toradex Colibri iMX7%c\n", 383ae440ab0SStefan Agner is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); 384ae440ab0SStefan Agner 385ae440ab0SStefan Agner return 0; 386ae440ab0SStefan Agner } 387ae440ab0SStefan Agner 38837fa4125SStefan Agner #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 38937fa4125SStefan Agner int ft_board_setup(void *blob, bd_t *bd) 39037fa4125SStefan Agner { 39164095704SStefan Agner #if defined(CONFIG_FDT_FIXUP_PARTITIONS) 392*b35fb6acSMasahiro Yamada static const struct node_info nodes[] = { 39364095704SStefan Agner { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 394e38adcecSStefan Agner { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, 39564095704SStefan Agner }; 39664095704SStefan Agner 39764095704SStefan Agner /* Update partition nodes using info from mtdparts env var */ 39864095704SStefan Agner puts(" Updating MTD partitions...\n"); 39964095704SStefan Agner fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 40064095704SStefan Agner #endif 40164095704SStefan Agner 40237fa4125SStefan Agner return ft_common_board_setup(blob, bd); 40337fa4125SStefan Agner } 40437fa4125SStefan Agner #endif 40537fa4125SStefan Agner 406ae440ab0SStefan Agner #ifdef CONFIG_USB_EHCI_MX7 407ae440ab0SStefan Agner static iomux_v3_cfg_t const usb_otg2_pads[] = { 408ae440ab0SStefan Agner MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 409ae440ab0SStefan Agner }; 410ae440ab0SStefan Agner 411ae440ab0SStefan Agner int board_ehci_hcd_init(int port) 412ae440ab0SStefan Agner { 413ae440ab0SStefan Agner switch (port) { 414ae440ab0SStefan Agner case 0: 415ae440ab0SStefan Agner break; 416ae440ab0SStefan Agner case 1: 417ae440ab0SStefan Agner if (is_cpu_type(MXC_CPU_MX7S)) 418ae440ab0SStefan Agner return -ENODEV; 419ae440ab0SStefan Agner 420ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 421ae440ab0SStefan Agner ARRAY_SIZE(usb_otg2_pads)); 422ae440ab0SStefan Agner break; 423ae440ab0SStefan Agner default: 424ae440ab0SStefan Agner return -EINVAL; 425ae440ab0SStefan Agner } 426ae440ab0SStefan Agner return 0; 427ae440ab0SStefan Agner } 4285a986dfeSStefan Agner 4295a986dfeSStefan Agner int board_usb_phy_mode(int port) 4305a986dfeSStefan Agner { 4315a986dfeSStefan Agner switch (port) { 4325a986dfeSStefan Agner case 0: 4335a986dfeSStefan Agner if (gpio_get_value(USB_CDET_GPIO)) 4345a986dfeSStefan Agner return USB_INIT_DEVICE; 4355a986dfeSStefan Agner else 4365a986dfeSStefan Agner return USB_INIT_HOST; 4375a986dfeSStefan Agner case 1: 4385a986dfeSStefan Agner default: 4395a986dfeSStefan Agner return USB_INIT_HOST; 4405a986dfeSStefan Agner } 4415a986dfeSStefan Agner } 442ae440ab0SStefan Agner #endif 443