183d290c5STom Rini // SPDX-License-Identifier: GPL-2.0+ 2ae440ab0SStefan Agner /* 3a62c6061SStefan Agner * Copyright (C) 2016-2018 Toradex AG 4ae440ab0SStefan Agner */ 5ae440ab0SStefan Agner 6ae440ab0SStefan Agner #include <asm/arch/clock.h> 7ae440ab0SStefan Agner #include <asm/arch/crm_regs.h> 8ae440ab0SStefan Agner #include <asm/arch/imx-regs.h> 9ae440ab0SStefan Agner #include <asm/arch/mx7-pins.h> 10ae440ab0SStefan Agner #include <asm/arch/sys_proto.h> 11ae440ab0SStefan Agner #include <asm/gpio.h> 12552a848eSStefano Babic #include <asm/mach-imx/iomux-v3.h> 13ae440ab0SStefan Agner #include <asm/io.h> 14ae440ab0SStefan Agner #include <common.h> 15ae440ab0SStefan Agner #include <dm.h> 16ae440ab0SStefan Agner #include <dm/platform_data/serial_mxc.h> 1764095704SStefan Agner #include <fdt_support.h> 18ae440ab0SStefan Agner #include <fsl_esdhc.h> 1964095704SStefan Agner #include <jffs2/load_kernel.h> 20ae440ab0SStefan Agner #include <linux/sizes.h> 21ae440ab0SStefan Agner #include <mmc.h> 22ae440ab0SStefan Agner #include <miiphy.h> 2364095704SStefan Agner #include <mtd_node.h> 24ae440ab0SStefan Agner #include <netdev.h> 2502ad90ecSStefan Agner #include <power/pmic.h> 2602ad90ecSStefan Agner #include <power/rn5t567_pmic.h> 275a986dfeSStefan Agner #include <usb.h> 28ae440ab0SStefan Agner #include <usb/ehci-ci.h> 2937fa4125SStefan Agner #include "../common/tdx-common.h" 30ae440ab0SStefan Agner 31ae440ab0SStefan Agner DECLARE_GLOBAL_DATA_PTR; 32ae440ab0SStefan Agner 33ae440ab0SStefan Agner #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 34ae440ab0SStefan Agner PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 35ae440ab0SStefan Agner 36ae440ab0SStefan Agner #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 37ae440ab0SStefan Agner #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 38ae440ab0SStefan Agner 39ae440ab0SStefan Agner #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 40ae440ab0SStefan Agner 41ae440ab0SStefan Agner #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 42ae440ab0SStefan Agner PAD_CTL_DSE_3P3V_49OHM) 43ae440ab0SStefan Agner 44ae440ab0SStefan Agner #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 45ae440ab0SStefan Agner 46ae440ab0SStefan Agner #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 47ae440ab0SStefan Agner 485a986dfeSStefan Agner #define USB_CDET_GPIO IMX_GPIO_NR(7, 14) 495a986dfeSStefan Agner 50ae440ab0SStefan Agner int dram_init(void) 51ae440ab0SStefan Agner { 52787075e0SFabio Estevam gd->ram_size = get_ram_size((void *)PHYS_SDRAM, imx_ddr_size()); 53ae440ab0SStefan Agner 54ae440ab0SStefan Agner return 0; 55ae440ab0SStefan Agner } 56ae440ab0SStefan Agner 57ae440ab0SStefan Agner static iomux_v3_cfg_t const uart1_pads[] = { 58ae440ab0SStefan Agner MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 59ae440ab0SStefan Agner MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 60ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 61ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 62ae440ab0SStefan Agner }; 63ae440ab0SStefan Agner 645a986dfeSStefan Agner #ifdef CONFIG_USB_EHCI_MX7 655a986dfeSStefan Agner static iomux_v3_cfg_t const usb_cdet_pads[] = { 665a986dfeSStefan Agner MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 675a986dfeSStefan Agner }; 685a986dfeSStefan Agner #endif 695a986dfeSStefan Agner 70a62c6061SStefan Agner #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND 71ae440ab0SStefan Agner static iomux_v3_cfg_t const gpmi_pads[] = { 72ae440ab0SStefan Agner MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 73ae440ab0SStefan Agner MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 74ae440ab0SStefan Agner MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 75ae440ab0SStefan Agner MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 76ae440ab0SStefan Agner MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 77ae440ab0SStefan Agner MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 78ae440ab0SStefan Agner MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 79ae440ab0SStefan Agner MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 80ae440ab0SStefan Agner MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 81ae440ab0SStefan Agner MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 82ae440ab0SStefan Agner MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 83ae440ab0SStefan Agner MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 84ae440ab0SStefan Agner MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 85ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 86ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 87ae440ab0SStefan Agner }; 88ae440ab0SStefan Agner 89ae440ab0SStefan Agner static void setup_gpmi_nand(void) 90ae440ab0SStefan Agner { 91ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 92ae440ab0SStefan Agner 93ae440ab0SStefan Agner /* NAND_USDHC_BUS_CLK is set in rom */ 94ae440ab0SStefan Agner set_clk_nand(); 95ae440ab0SStefan Agner } 96ae440ab0SStefan Agner #endif 97ae440ab0SStefan Agner 98ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 99ae440ab0SStefan Agner static iomux_v3_cfg_t const lcd_pads[] = { 100ae440ab0SStefan Agner MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 101ae440ab0SStefan Agner MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 102ae440ab0SStefan Agner MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 103ae440ab0SStefan Agner MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 104ae440ab0SStefan Agner MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 105ae440ab0SStefan Agner MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 106ae440ab0SStefan Agner MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 107ae440ab0SStefan Agner MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 108ae440ab0SStefan Agner MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 109ae440ab0SStefan Agner MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 110ae440ab0SStefan Agner MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 111ae440ab0SStefan Agner MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 112ae440ab0SStefan Agner MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 113ae440ab0SStefan Agner MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 114ae440ab0SStefan Agner MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 115ae440ab0SStefan Agner MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 116ae440ab0SStefan Agner MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 117ae440ab0SStefan Agner MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 118ae440ab0SStefan Agner MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 119ae440ab0SStefan Agner MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 120ae440ab0SStefan Agner MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 121ae440ab0SStefan Agner MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 122ae440ab0SStefan Agner }; 123ae440ab0SStefan Agner 124ae440ab0SStefan Agner static iomux_v3_cfg_t const backlight_pads[] = { 125ae440ab0SStefan Agner /* Backlight On */ 126ae440ab0SStefan Agner MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 127ae440ab0SStefan Agner /* Backlight PWM<A> (multiplexed pin) */ 128ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), 129ae440ab0SStefan Agner MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 130ae440ab0SStefan Agner }; 131ae440ab0SStefan Agner 132ae440ab0SStefan Agner #define GPIO_BL_ON IMX_GPIO_NR(5, 1) 133ae440ab0SStefan Agner #define GPIO_PWM_A IMX_GPIO_NR(1, 8) 134ae440ab0SStefan Agner 135ae440ab0SStefan Agner static int setup_lcd(void) 136ae440ab0SStefan Agner { 137ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 138ae440ab0SStefan Agner 139ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); 140ae440ab0SStefan Agner 141ae440ab0SStefan Agner /* Set BL_ON */ 142ae440ab0SStefan Agner gpio_request(GPIO_BL_ON, "BL_ON"); 143ae440ab0SStefan Agner gpio_direction_output(GPIO_BL_ON, 1); 144ae440ab0SStefan Agner 145ae440ab0SStefan Agner /* Set PWM<A> to full brightness (assuming inversed polarity) */ 146ae440ab0SStefan Agner gpio_request(GPIO_PWM_A, "PWM<A>"); 147ae440ab0SStefan Agner gpio_direction_output(GPIO_PWM_A, 0); 148ae440ab0SStefan Agner 149ae440ab0SStefan Agner return 0; 150ae440ab0SStefan Agner } 151ae440ab0SStefan Agner #endif 152ae440ab0SStefan Agner 153*a3c90217SGerard Salvatella /* 154*a3c90217SGerard Salvatella * Backlight off before OS handover 155*a3c90217SGerard Salvatella */ 156*a3c90217SGerard Salvatella void board_preboot_os(void) 157*a3c90217SGerard Salvatella { 158*a3c90217SGerard Salvatella gpio_direction_output(GPIO_PWM_A, 1); 159*a3c90217SGerard Salvatella gpio_direction_output(GPIO_BL_ON, 0); 160*a3c90217SGerard Salvatella } 161*a3c90217SGerard Salvatella 162ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 163ae440ab0SStefan Agner static iomux_v3_cfg_t const fec1_pads[] = { 164ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 165ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, 166ae440ab0SStefan Agner #else 167ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 168ae440ab0SStefan Agner #endif 169ae440ab0SStefan Agner MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 170ae440ab0SStefan Agner MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 171ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 172ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 173ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 174ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 175ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 176ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 177ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 178ae440ab0SStefan Agner }; 179ae440ab0SStefan Agner 180ae440ab0SStefan Agner static void setup_iomux_fec(void) 181ae440ab0SStefan Agner { 182ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 183ae440ab0SStefan Agner } 184ae440ab0SStefan Agner #endif 185ae440ab0SStefan Agner 186ae440ab0SStefan Agner static void setup_iomux_uart(void) 187ae440ab0SStefan Agner { 188ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 189ae440ab0SStefan Agner } 190ae440ab0SStefan Agner 191ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 192ae440ab0SStefan Agner int board_eth_init(bd_t *bis) 193ae440ab0SStefan Agner { 194ae440ab0SStefan Agner int ret; 195ae440ab0SStefan Agner 196ae440ab0SStefan Agner setup_iomux_fec(); 197ae440ab0SStefan Agner 198ae440ab0SStefan Agner ret = fecmxc_initialize_multi(bis, 0, 199ae440ab0SStefan Agner CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 200ae440ab0SStefan Agner if (ret) 201ae440ab0SStefan Agner printf("FEC1 MXC: %s:failed\n", __func__); 202ae440ab0SStefan Agner 203ae440ab0SStefan Agner return ret; 204ae440ab0SStefan Agner } 205ae440ab0SStefan Agner 206ae440ab0SStefan Agner static int setup_fec(void) 207ae440ab0SStefan Agner { 208ae440ab0SStefan Agner struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 209ae440ab0SStefan Agner = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 210ae440ab0SStefan Agner 211ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 212ae440ab0SStefan Agner /* 213ae440ab0SStefan Agner * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] 214ae440ab0SStefan Agner * and output it on the pin 215ae440ab0SStefan Agner */ 216ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 217ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 218ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); 219ae440ab0SStefan Agner #else 220ae440ab0SStefan Agner /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ 221ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 222ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 223ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); 224ae440ab0SStefan Agner #endif 225ae440ab0SStefan Agner 2268590786aSEric Nelson return set_clk_enet(ENET_50MHZ); 227ae440ab0SStefan Agner } 228ae440ab0SStefan Agner 229ae440ab0SStefan Agner int board_phy_config(struct phy_device *phydev) 230ae440ab0SStefan Agner { 231ae440ab0SStefan Agner if (phydev->drv->config) 232ae440ab0SStefan Agner phydev->drv->config(phydev); 233ae440ab0SStefan Agner return 0; 234ae440ab0SStefan Agner } 235ae440ab0SStefan Agner #endif 236ae440ab0SStefan Agner 237ae440ab0SStefan Agner int board_early_init_f(void) 238ae440ab0SStefan Agner { 239ae440ab0SStefan Agner setup_iomux_uart(); 240ae440ab0SStefan Agner 241ae440ab0SStefan Agner return 0; 242ae440ab0SStefan Agner } 243ae440ab0SStefan Agner 244ae440ab0SStefan Agner int board_init(void) 245ae440ab0SStefan Agner { 246ae440ab0SStefan Agner /* address of boot parameters */ 247ae440ab0SStefan Agner gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 248ae440ab0SStefan Agner 249ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 250ae440ab0SStefan Agner setup_fec(); 251ae440ab0SStefan Agner #endif 252ae440ab0SStefan Agner 253a62c6061SStefan Agner #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND 254ae440ab0SStefan Agner setup_gpmi_nand(); 255ae440ab0SStefan Agner #endif 256ae440ab0SStefan Agner 257ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 258ae440ab0SStefan Agner setup_lcd(); 259ae440ab0SStefan Agner #endif 260ae440ab0SStefan Agner 2615a986dfeSStefan Agner #ifdef CONFIG_USB_EHCI_MX7 2625a986dfeSStefan Agner imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); 2635a986dfeSStefan Agner gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); 2645a986dfeSStefan Agner #endif 2655a986dfeSStefan Agner 266ae440ab0SStefan Agner return 0; 267ae440ab0SStefan Agner } 268ae440ab0SStefan Agner 26902ad90ecSStefan Agner #ifdef CONFIG_DM_PMIC 27002ad90ecSStefan Agner int power_init_board(void) 27102ad90ecSStefan Agner { 27202ad90ecSStefan Agner struct udevice *dev; 27302ad90ecSStefan Agner int reg, ver; 27402ad90ecSStefan Agner int ret; 27502ad90ecSStefan Agner 27602ad90ecSStefan Agner 27702ad90ecSStefan Agner ret = pmic_get("rn5t567", &dev); 27802ad90ecSStefan Agner if (ret) 27902ad90ecSStefan Agner return ret; 28002ad90ecSStefan Agner ver = pmic_reg_read(dev, RN5T567_LSIVER); 28102ad90ecSStefan Agner reg = pmic_reg_read(dev, RN5T567_OTPVER); 28202ad90ecSStefan Agner 28302ad90ecSStefan Agner printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); 28402ad90ecSStefan Agner 28502ad90ecSStefan Agner /* set judge and press timer of N_OE to minimal values */ 28602ad90ecSStefan Agner pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); 28702ad90ecSStefan Agner 28805ed964dSStefan Agner /* configure sleep slot for 3.3V Ethernet */ 28905ed964dSStefan Agner reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT); 29005ed964dSStefan Agner reg = (reg & 0xf0) | reg >> 4; 29105ed964dSStefan Agner pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg); 29205ed964dSStefan Agner 29305ed964dSStefan Agner /* disable DCDC2 discharge to avoid backfeeding through VFB2 */ 29405ed964dSStefan Agner pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); 29505ed964dSStefan Agner 29605ed964dSStefan Agner /* configure sleep slot for ARM rail */ 29705ed964dSStefan Agner reg = pmic_reg_read(dev, RN5T567_DC2_SLOT); 29805ed964dSStefan Agner reg = (reg & 0xf0) | reg >> 4; 29905ed964dSStefan Agner pmic_reg_write(dev, RN5T567_DC2_SLOT, reg); 30005ed964dSStefan Agner 30105ed964dSStefan Agner /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */ 30205ed964dSStefan Agner pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); 30305ed964dSStefan Agner 30402ad90ecSStefan Agner return 0; 30502ad90ecSStefan Agner } 30602ad90ecSStefan Agner 30702ad90ecSStefan Agner void reset_cpu(ulong addr) 30802ad90ecSStefan Agner { 30902ad90ecSStefan Agner struct udevice *dev; 31002ad90ecSStefan Agner 31102ad90ecSStefan Agner pmic_get("rn5t567", &dev); 31202ad90ecSStefan Agner 31302ad90ecSStefan Agner /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ 31402ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_REPCNT, 0x1); 31502ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); 31602ad90ecSStefan Agner 31702ad90ecSStefan Agner /* 31802ad90ecSStefan Agner * Re-power factor detection on PMIC side is not instant. 1ms 31902ad90ecSStefan Agner * proved to be enough time until reset takes effect. 32002ad90ecSStefan Agner */ 32102ad90ecSStefan Agner mdelay(1); 32202ad90ecSStefan Agner } 32302ad90ecSStefan Agner #endif 32402ad90ecSStefan Agner 325ae440ab0SStefan Agner int checkboard(void) 326ae440ab0SStefan Agner { 327ae440ab0SStefan Agner printf("Model: Toradex Colibri iMX7%c\n", 328ae440ab0SStefan Agner is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); 329ae440ab0SStefan Agner 330ae440ab0SStefan Agner return 0; 331ae440ab0SStefan Agner } 332ae440ab0SStefan Agner 33337fa4125SStefan Agner #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 33437fa4125SStefan Agner int ft_board_setup(void *blob, bd_t *bd) 33537fa4125SStefan Agner { 33664095704SStefan Agner #if defined(CONFIG_FDT_FIXUP_PARTITIONS) 337b35fb6acSMasahiro Yamada static const struct node_info nodes[] = { 33864095704SStefan Agner { "fsl,imx7d-gpmi-nand", MTD_DEV_TYPE_NAND, }, /* NAND flash */ 339e38adcecSStefan Agner { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, 34064095704SStefan Agner }; 34164095704SStefan Agner 34264095704SStefan Agner /* Update partition nodes using info from mtdparts env var */ 34364095704SStefan Agner puts(" Updating MTD partitions...\n"); 34464095704SStefan Agner fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 34564095704SStefan Agner #endif 34664095704SStefan Agner 34737fa4125SStefan Agner return ft_common_board_setup(blob, bd); 34837fa4125SStefan Agner } 34937fa4125SStefan Agner #endif 35037fa4125SStefan Agner 351ae440ab0SStefan Agner #ifdef CONFIG_USB_EHCI_MX7 352ae440ab0SStefan Agner static iomux_v3_cfg_t const usb_otg2_pads[] = { 353ae440ab0SStefan Agner MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 354ae440ab0SStefan Agner }; 355ae440ab0SStefan Agner 356ae440ab0SStefan Agner int board_ehci_hcd_init(int port) 357ae440ab0SStefan Agner { 358ae440ab0SStefan Agner switch (port) { 359ae440ab0SStefan Agner case 0: 360ae440ab0SStefan Agner break; 361ae440ab0SStefan Agner case 1: 362ae440ab0SStefan Agner if (is_cpu_type(MXC_CPU_MX7S)) 363ae440ab0SStefan Agner return -ENODEV; 364ae440ab0SStefan Agner 365ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 366ae440ab0SStefan Agner ARRAY_SIZE(usb_otg2_pads)); 367ae440ab0SStefan Agner break; 368ae440ab0SStefan Agner default: 369ae440ab0SStefan Agner return -EINVAL; 370ae440ab0SStefan Agner } 371ae440ab0SStefan Agner return 0; 372ae440ab0SStefan Agner } 3735a986dfeSStefan Agner 3745a986dfeSStefan Agner int board_usb_phy_mode(int port) 3755a986dfeSStefan Agner { 3765a986dfeSStefan Agner switch (port) { 3775a986dfeSStefan Agner case 0: 3785a986dfeSStefan Agner if (gpio_get_value(USB_CDET_GPIO)) 3795a986dfeSStefan Agner return USB_INIT_DEVICE; 3805a986dfeSStefan Agner else 3815a986dfeSStefan Agner return USB_INIT_HOST; 3825a986dfeSStefan Agner case 1: 3835a986dfeSStefan Agner default: 3845a986dfeSStefan Agner return USB_INIT_HOST; 3855a986dfeSStefan Agner } 3865a986dfeSStefan Agner } 387ae440ab0SStefan Agner #endif 388