1ae440ab0SStefan Agner /* 2ae440ab0SStefan Agner * Copyright (C) 2016 Toradex AG 3ae440ab0SStefan Agner * 4ae440ab0SStefan Agner * SPDX-License-Identifier: GPL-2.0+ 5ae440ab0SStefan Agner */ 6ae440ab0SStefan Agner 7ae440ab0SStefan Agner #include <asm/arch/clock.h> 8ae440ab0SStefan Agner #include <asm/arch/crm_regs.h> 9ae440ab0SStefan Agner #include <asm/arch/imx-regs.h> 10ae440ab0SStefan Agner #include <asm/arch/mx7-pins.h> 11ae440ab0SStefan Agner #include <asm/arch/sys_proto.h> 12ae440ab0SStefan Agner #include <asm/gpio.h> 13ae440ab0SStefan Agner #include <asm/imx-common/boot_mode.h> 14ae440ab0SStefan Agner #include <asm/imx-common/iomux-v3.h> 15ae440ab0SStefan Agner #include <asm/io.h> 16ae440ab0SStefan Agner #include <common.h> 17ae440ab0SStefan Agner #include <dm.h> 18ae440ab0SStefan Agner #include <dm/platform_data/serial_mxc.h> 19ae440ab0SStefan Agner #include <fsl_esdhc.h> 20ae440ab0SStefan Agner #include <linux/sizes.h> 21ae440ab0SStefan Agner #include <mmc.h> 22ae440ab0SStefan Agner #include <miiphy.h> 23ae440ab0SStefan Agner #include <netdev.h> 2402ad90ecSStefan Agner #include <power/pmic.h> 2502ad90ecSStefan Agner #include <power/rn5t567_pmic.h> 26ae440ab0SStefan Agner #include <usb/ehci-ci.h> 27*37fa4125SStefan Agner #include "../common/tdx-common.h" 28ae440ab0SStefan Agner 29ae440ab0SStefan Agner DECLARE_GLOBAL_DATA_PTR; 30ae440ab0SStefan Agner 31ae440ab0SStefan Agner #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 32ae440ab0SStefan Agner PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 33ae440ab0SStefan Agner 34ae440ab0SStefan Agner #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 35ae440ab0SStefan Agner PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 36ae440ab0SStefan Agner 37ae440ab0SStefan Agner #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 38ae440ab0SStefan Agner #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 39ae440ab0SStefan Agner 40ae440ab0SStefan Agner #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 41ae440ab0SStefan Agner 42ae440ab0SStefan Agner #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 43ae440ab0SStefan Agner PAD_CTL_DSE_3P3V_49OHM) 44ae440ab0SStefan Agner 45ae440ab0SStefan Agner #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 46ae440ab0SStefan Agner 47ae440ab0SStefan Agner #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 48ae440ab0SStefan Agner 49ae440ab0SStefan Agner int dram_init(void) 50ae440ab0SStefan Agner { 51ae440ab0SStefan Agner gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 52ae440ab0SStefan Agner 53ae440ab0SStefan Agner return 0; 54ae440ab0SStefan Agner } 55ae440ab0SStefan Agner 56ae440ab0SStefan Agner static iomux_v3_cfg_t const uart1_pads[] = { 57ae440ab0SStefan Agner MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 58ae440ab0SStefan Agner MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 59ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 60ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 61ae440ab0SStefan Agner }; 62ae440ab0SStefan Agner 63ae440ab0SStefan Agner static iomux_v3_cfg_t const usdhc1_pads[] = { 64ae440ab0SStefan Agner MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 65ae440ab0SStefan Agner MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 66ae440ab0SStefan Agner MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 67ae440ab0SStefan Agner MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68ae440ab0SStefan Agner MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69ae440ab0SStefan Agner MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70ae440ab0SStefan Agner 71ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), 72ae440ab0SStefan Agner }; 73ae440ab0SStefan Agner 74ae440ab0SStefan Agner #ifdef CONFIG_NAND_MXS 75ae440ab0SStefan Agner static iomux_v3_cfg_t const gpmi_pads[] = { 76ae440ab0SStefan Agner MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 77ae440ab0SStefan Agner MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 78ae440ab0SStefan Agner MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 79ae440ab0SStefan Agner MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 80ae440ab0SStefan Agner MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 81ae440ab0SStefan Agner MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 82ae440ab0SStefan Agner MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 83ae440ab0SStefan Agner MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 84ae440ab0SStefan Agner MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 85ae440ab0SStefan Agner MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 86ae440ab0SStefan Agner MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 87ae440ab0SStefan Agner MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 88ae440ab0SStefan Agner MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 89ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 90ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 91ae440ab0SStefan Agner }; 92ae440ab0SStefan Agner 93ae440ab0SStefan Agner static void setup_gpmi_nand(void) 94ae440ab0SStefan Agner { 95ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 96ae440ab0SStefan Agner 97ae440ab0SStefan Agner /* NAND_USDHC_BUS_CLK is set in rom */ 98ae440ab0SStefan Agner set_clk_nand(); 99ae440ab0SStefan Agner } 100ae440ab0SStefan Agner #endif 101ae440ab0SStefan Agner 102ae440ab0SStefan Agner static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 103ae440ab0SStefan Agner MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 104ae440ab0SStefan Agner MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 105ae440ab0SStefan Agner MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 106ae440ab0SStefan Agner MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 107ae440ab0SStefan Agner MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 108ae440ab0SStefan Agner MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 109ae440ab0SStefan Agner MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 110ae440ab0SStefan Agner MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 111ae440ab0SStefan Agner MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 112ae440ab0SStefan Agner MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113ae440ab0SStefan Agner MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114ae440ab0SStefan Agner 115ae440ab0SStefan Agner MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116ae440ab0SStefan Agner }; 117ae440ab0SStefan Agner 118ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 119ae440ab0SStefan Agner static iomux_v3_cfg_t const lcd_pads[] = { 120ae440ab0SStefan Agner MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 121ae440ab0SStefan Agner MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 122ae440ab0SStefan Agner MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 123ae440ab0SStefan Agner MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 124ae440ab0SStefan Agner MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 125ae440ab0SStefan Agner MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 126ae440ab0SStefan Agner MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 127ae440ab0SStefan Agner MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 128ae440ab0SStefan Agner MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 129ae440ab0SStefan Agner MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 130ae440ab0SStefan Agner MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 131ae440ab0SStefan Agner MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 132ae440ab0SStefan Agner MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 133ae440ab0SStefan Agner MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134ae440ab0SStefan Agner MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135ae440ab0SStefan Agner MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136ae440ab0SStefan Agner MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 137ae440ab0SStefan Agner MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 138ae440ab0SStefan Agner MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 139ae440ab0SStefan Agner MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 140ae440ab0SStefan Agner MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 141ae440ab0SStefan Agner MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 142ae440ab0SStefan Agner }; 143ae440ab0SStefan Agner 144ae440ab0SStefan Agner static iomux_v3_cfg_t const backlight_pads[] = { 145ae440ab0SStefan Agner /* Backlight On */ 146ae440ab0SStefan Agner MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 147ae440ab0SStefan Agner /* Backlight PWM<A> (multiplexed pin) */ 148ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), 149ae440ab0SStefan Agner MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 150ae440ab0SStefan Agner }; 151ae440ab0SStefan Agner 152ae440ab0SStefan Agner #define GPIO_BL_ON IMX_GPIO_NR(5, 1) 153ae440ab0SStefan Agner #define GPIO_PWM_A IMX_GPIO_NR(1, 8) 154ae440ab0SStefan Agner 155ae440ab0SStefan Agner static int setup_lcd(void) 156ae440ab0SStefan Agner { 157ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 158ae440ab0SStefan Agner 159ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); 160ae440ab0SStefan Agner 161ae440ab0SStefan Agner /* Set BL_ON */ 162ae440ab0SStefan Agner gpio_request(GPIO_BL_ON, "BL_ON"); 163ae440ab0SStefan Agner gpio_direction_output(GPIO_BL_ON, 1); 164ae440ab0SStefan Agner 165ae440ab0SStefan Agner /* Set PWM<A> to full brightness (assuming inversed polarity) */ 166ae440ab0SStefan Agner gpio_request(GPIO_PWM_A, "PWM<A>"); 167ae440ab0SStefan Agner gpio_direction_output(GPIO_PWM_A, 0); 168ae440ab0SStefan Agner 169ae440ab0SStefan Agner return 0; 170ae440ab0SStefan Agner } 171ae440ab0SStefan Agner #endif 172ae440ab0SStefan Agner 173ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 174ae440ab0SStefan Agner static iomux_v3_cfg_t const fec1_pads[] = { 175ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 176ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, 177ae440ab0SStefan Agner #else 178ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 179ae440ab0SStefan Agner #endif 180ae440ab0SStefan Agner MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 181ae440ab0SStefan Agner MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 182ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 183ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 184ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 185ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 186ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 187ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 188ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 189ae440ab0SStefan Agner }; 190ae440ab0SStefan Agner 191ae440ab0SStefan Agner static void setup_iomux_fec(void) 192ae440ab0SStefan Agner { 193ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 194ae440ab0SStefan Agner } 195ae440ab0SStefan Agner #endif 196ae440ab0SStefan Agner 197ae440ab0SStefan Agner static void setup_iomux_uart(void) 198ae440ab0SStefan Agner { 199ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 200ae440ab0SStefan Agner } 201ae440ab0SStefan Agner 202ae440ab0SStefan Agner #ifdef CONFIG_FSL_ESDHC 203ae440ab0SStefan Agner 204ae440ab0SStefan Agner #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) 205ae440ab0SStefan Agner 206ae440ab0SStefan Agner static struct fsl_esdhc_cfg usdhc_cfg[] = { 207ae440ab0SStefan Agner {USDHC1_BASE_ADDR, 0, 4}, 208ae440ab0SStefan Agner }; 209ae440ab0SStefan Agner 210ae440ab0SStefan Agner int board_mmc_getcd(struct mmc *mmc) 211ae440ab0SStefan Agner { 212ae440ab0SStefan Agner struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 213ae440ab0SStefan Agner int ret = 0; 214ae440ab0SStefan Agner 215ae440ab0SStefan Agner switch (cfg->esdhc_base) { 216ae440ab0SStefan Agner case USDHC1_BASE_ADDR: 217ae440ab0SStefan Agner ret = !gpio_get_value(USDHC1_CD_GPIO); 218ae440ab0SStefan Agner break; 219ae440ab0SStefan Agner } 220ae440ab0SStefan Agner 221ae440ab0SStefan Agner return ret; 222ae440ab0SStefan Agner } 223ae440ab0SStefan Agner 224ae440ab0SStefan Agner int board_mmc_init(bd_t *bis) 225ae440ab0SStefan Agner { 226ae440ab0SStefan Agner int i, ret; 227ae440ab0SStefan Agner /* USDHC1 is mmc0 */ 228ae440ab0SStefan Agner for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 229ae440ab0SStefan Agner switch (i) { 230ae440ab0SStefan Agner case 0: 231ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads( 232ae440ab0SStefan Agner usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 233ae440ab0SStefan Agner gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 234ae440ab0SStefan Agner gpio_direction_input(USDHC1_CD_GPIO); 235ae440ab0SStefan Agner usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 236ae440ab0SStefan Agner break; 237ae440ab0SStefan Agner default: 238ae440ab0SStefan Agner printf("Warning: you configured more USDHC controllers" 239ae440ab0SStefan Agner "(%d) than supported by the board\n", i + 1); 240ae440ab0SStefan Agner return -EINVAL; 241ae440ab0SStefan Agner } 242ae440ab0SStefan Agner 243ae440ab0SStefan Agner ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 244ae440ab0SStefan Agner if (ret) 245ae440ab0SStefan Agner return ret; 246ae440ab0SStefan Agner } 247ae440ab0SStefan Agner 248ae440ab0SStefan Agner return 0; 249ae440ab0SStefan Agner } 250ae440ab0SStefan Agner #endif 251ae440ab0SStefan Agner 252ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 253ae440ab0SStefan Agner int board_eth_init(bd_t *bis) 254ae440ab0SStefan Agner { 255ae440ab0SStefan Agner int ret; 256ae440ab0SStefan Agner 257ae440ab0SStefan Agner setup_iomux_fec(); 258ae440ab0SStefan Agner 259ae440ab0SStefan Agner ret = fecmxc_initialize_multi(bis, 0, 260ae440ab0SStefan Agner CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 261ae440ab0SStefan Agner if (ret) 262ae440ab0SStefan Agner printf("FEC1 MXC: %s:failed\n", __func__); 263ae440ab0SStefan Agner 264ae440ab0SStefan Agner return ret; 265ae440ab0SStefan Agner } 266ae440ab0SStefan Agner 267ae440ab0SStefan Agner static int setup_fec(void) 268ae440ab0SStefan Agner { 269ae440ab0SStefan Agner struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 270ae440ab0SStefan Agner = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 271ae440ab0SStefan Agner 272ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 273ae440ab0SStefan Agner /* 274ae440ab0SStefan Agner * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] 275ae440ab0SStefan Agner * and output it on the pin 276ae440ab0SStefan Agner */ 277ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 278ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 279ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); 280ae440ab0SStefan Agner #else 281ae440ab0SStefan Agner /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ 282ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 283ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 284ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); 285ae440ab0SStefan Agner #endif 286ae440ab0SStefan Agner 287ae440ab0SStefan Agner return set_clk_enet(ENET_50MHz); 288ae440ab0SStefan Agner } 289ae440ab0SStefan Agner 290ae440ab0SStefan Agner int board_phy_config(struct phy_device *phydev) 291ae440ab0SStefan Agner { 292ae440ab0SStefan Agner if (phydev->drv->config) 293ae440ab0SStefan Agner phydev->drv->config(phydev); 294ae440ab0SStefan Agner return 0; 295ae440ab0SStefan Agner } 296ae440ab0SStefan Agner #endif 297ae440ab0SStefan Agner 298ae440ab0SStefan Agner int board_early_init_f(void) 299ae440ab0SStefan Agner { 300ae440ab0SStefan Agner setup_iomux_uart(); 301ae440ab0SStefan Agner 302ae440ab0SStefan Agner return 0; 303ae440ab0SStefan Agner } 304ae440ab0SStefan Agner 305ae440ab0SStefan Agner int board_init(void) 306ae440ab0SStefan Agner { 307ae440ab0SStefan Agner /* address of boot parameters */ 308ae440ab0SStefan Agner gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 309ae440ab0SStefan Agner 310ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 311ae440ab0SStefan Agner setup_fec(); 312ae440ab0SStefan Agner #endif 313ae440ab0SStefan Agner 314ae440ab0SStefan Agner #ifdef CONFIG_NAND_MXS 315ae440ab0SStefan Agner setup_gpmi_nand(); 316ae440ab0SStefan Agner #endif 317ae440ab0SStefan Agner 318ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 319ae440ab0SStefan Agner setup_lcd(); 320ae440ab0SStefan Agner #endif 321ae440ab0SStefan Agner 322ae440ab0SStefan Agner return 0; 323ae440ab0SStefan Agner } 324ae440ab0SStefan Agner 325ae440ab0SStefan Agner #ifdef CONFIG_CMD_BMODE 326ae440ab0SStefan Agner static const struct boot_mode board_boot_modes[] = { 327ae440ab0SStefan Agner /* 4 bit bus width */ 328ae440ab0SStefan Agner {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, 329ae440ab0SStefan Agner {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 330ae440ab0SStefan Agner {NULL, 0}, 331ae440ab0SStefan Agner }; 332ae440ab0SStefan Agner #endif 333ae440ab0SStefan Agner 334ae440ab0SStefan Agner int board_late_init(void) 335ae440ab0SStefan Agner { 336ae440ab0SStefan Agner #ifdef CONFIG_CMD_BMODE 337ae440ab0SStefan Agner add_board_boot_modes(board_boot_modes); 338ae440ab0SStefan Agner #endif 339ae440ab0SStefan Agner 340ae440ab0SStefan Agner return 0; 341ae440ab0SStefan Agner } 342ae440ab0SStefan Agner 34302ad90ecSStefan Agner #ifdef CONFIG_DM_PMIC 34402ad90ecSStefan Agner int power_init_board(void) 34502ad90ecSStefan Agner { 34602ad90ecSStefan Agner struct udevice *dev; 34702ad90ecSStefan Agner int reg, ver; 34802ad90ecSStefan Agner int ret; 34902ad90ecSStefan Agner 35002ad90ecSStefan Agner 35102ad90ecSStefan Agner ret = pmic_get("rn5t567", &dev); 35202ad90ecSStefan Agner if (ret) 35302ad90ecSStefan Agner return ret; 35402ad90ecSStefan Agner ver = pmic_reg_read(dev, RN5T567_LSIVER); 35502ad90ecSStefan Agner reg = pmic_reg_read(dev, RN5T567_OTPVER); 35602ad90ecSStefan Agner 35702ad90ecSStefan Agner printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); 35802ad90ecSStefan Agner 35902ad90ecSStefan Agner /* set judge and press timer of N_OE to minimal values */ 36002ad90ecSStefan Agner pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); 36102ad90ecSStefan Agner 36202ad90ecSStefan Agner return 0; 36302ad90ecSStefan Agner } 36402ad90ecSStefan Agner 36502ad90ecSStefan Agner void reset_cpu(ulong addr) 36602ad90ecSStefan Agner { 36702ad90ecSStefan Agner struct udevice *dev; 36802ad90ecSStefan Agner 36902ad90ecSStefan Agner pmic_get("rn5t567", &dev); 37002ad90ecSStefan Agner 37102ad90ecSStefan Agner /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ 37202ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_REPCNT, 0x1); 37302ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); 37402ad90ecSStefan Agner 37502ad90ecSStefan Agner /* 37602ad90ecSStefan Agner * Re-power factor detection on PMIC side is not instant. 1ms 37702ad90ecSStefan Agner * proved to be enough time until reset takes effect. 37802ad90ecSStefan Agner */ 37902ad90ecSStefan Agner mdelay(1); 38002ad90ecSStefan Agner } 38102ad90ecSStefan Agner #endif 38202ad90ecSStefan Agner 383ae440ab0SStefan Agner int checkboard(void) 384ae440ab0SStefan Agner { 385ae440ab0SStefan Agner printf("Model: Toradex Colibri iMX7%c\n", 386ae440ab0SStefan Agner is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); 387ae440ab0SStefan Agner 388ae440ab0SStefan Agner return 0; 389ae440ab0SStefan Agner } 390ae440ab0SStefan Agner 391*37fa4125SStefan Agner #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 392*37fa4125SStefan Agner int ft_board_setup(void *blob, bd_t *bd) 393*37fa4125SStefan Agner { 394*37fa4125SStefan Agner return ft_common_board_setup(blob, bd); 395*37fa4125SStefan Agner } 396*37fa4125SStefan Agner #endif 397*37fa4125SStefan Agner 398ae440ab0SStefan Agner #ifdef CONFIG_USB_EHCI_MX7 399ae440ab0SStefan Agner static iomux_v3_cfg_t const usb_otg2_pads[] = { 400ae440ab0SStefan Agner MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 401ae440ab0SStefan Agner }; 402ae440ab0SStefan Agner 403ae440ab0SStefan Agner int board_ehci_hcd_init(int port) 404ae440ab0SStefan Agner { 405ae440ab0SStefan Agner switch (port) { 406ae440ab0SStefan Agner case 0: 407ae440ab0SStefan Agner break; 408ae440ab0SStefan Agner case 1: 409ae440ab0SStefan Agner if (is_cpu_type(MXC_CPU_MX7S)) 410ae440ab0SStefan Agner return -ENODEV; 411ae440ab0SStefan Agner 412ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 413ae440ab0SStefan Agner ARRAY_SIZE(usb_otg2_pads)); 414ae440ab0SStefan Agner break; 415ae440ab0SStefan Agner default: 416ae440ab0SStefan Agner return -EINVAL; 417ae440ab0SStefan Agner } 418ae440ab0SStefan Agner return 0; 419ae440ab0SStefan Agner } 420ae440ab0SStefan Agner #endif 421