1ae440ab0SStefan Agner /* 2ae440ab0SStefan Agner * Copyright (C) 2016 Toradex AG 3ae440ab0SStefan Agner * 4ae440ab0SStefan Agner * SPDX-License-Identifier: GPL-2.0+ 5ae440ab0SStefan Agner */ 6ae440ab0SStefan Agner 7ae440ab0SStefan Agner #include <asm/arch/clock.h> 8ae440ab0SStefan Agner #include <asm/arch/crm_regs.h> 9ae440ab0SStefan Agner #include <asm/arch/imx-regs.h> 10ae440ab0SStefan Agner #include <asm/arch/mx7-pins.h> 11ae440ab0SStefan Agner #include <asm/arch/sys_proto.h> 12ae440ab0SStefan Agner #include <asm/gpio.h> 13ae440ab0SStefan Agner #include <asm/imx-common/boot_mode.h> 14ae440ab0SStefan Agner #include <asm/imx-common/iomux-v3.h> 15ae440ab0SStefan Agner #include <asm/io.h> 16ae440ab0SStefan Agner #include <common.h> 17ae440ab0SStefan Agner #include <dm.h> 18ae440ab0SStefan Agner #include <dm/platform_data/serial_mxc.h> 19ae440ab0SStefan Agner #include <fsl_esdhc.h> 20ae440ab0SStefan Agner #include <linux/sizes.h> 21ae440ab0SStefan Agner #include <mmc.h> 22ae440ab0SStefan Agner #include <miiphy.h> 23ae440ab0SStefan Agner #include <netdev.h> 2402ad90ecSStefan Agner #include <power/pmic.h> 2502ad90ecSStefan Agner #include <power/rn5t567_pmic.h> 265a986dfeSStefan Agner #include <usb.h> 27ae440ab0SStefan Agner #include <usb/ehci-ci.h> 2837fa4125SStefan Agner #include "../common/tdx-common.h" 29ae440ab0SStefan Agner 30ae440ab0SStefan Agner DECLARE_GLOBAL_DATA_PTR; 31ae440ab0SStefan Agner 32ae440ab0SStefan Agner #define UART_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | \ 33ae440ab0SStefan Agner PAD_CTL_PUS_PU100KOHM | PAD_CTL_HYS) 34ae440ab0SStefan Agner 35ae440ab0SStefan Agner #define USDHC_PAD_CTRL (PAD_CTL_DSE_3P3V_32OHM | PAD_CTL_SRE_SLOW | \ 36ae440ab0SStefan Agner PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM) 37ae440ab0SStefan Agner 38ae440ab0SStefan Agner #define ENET_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 39ae440ab0SStefan Agner #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_3P3V_32OHM) 40ae440ab0SStefan Agner 41ae440ab0SStefan Agner #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_PU100KOHM | PAD_CTL_DSE_3P3V_49OHM) 42ae440ab0SStefan Agner 43ae440ab0SStefan Agner #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_PU100KOHM | \ 44ae440ab0SStefan Agner PAD_CTL_DSE_3P3V_49OHM) 45ae440ab0SStefan Agner 46ae440ab0SStefan Agner #define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 47ae440ab0SStefan Agner 48ae440ab0SStefan Agner #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM) 49ae440ab0SStefan Agner 505a986dfeSStefan Agner #define USB_CDET_GPIO IMX_GPIO_NR(7, 14) 515a986dfeSStefan Agner 52ae440ab0SStefan Agner int dram_init(void) 53ae440ab0SStefan Agner { 54ae440ab0SStefan Agner gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 55ae440ab0SStefan Agner 56ae440ab0SStefan Agner return 0; 57ae440ab0SStefan Agner } 58ae440ab0SStefan Agner 59ae440ab0SStefan Agner static iomux_v3_cfg_t const uart1_pads[] = { 60ae440ab0SStefan Agner MX7D_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 61ae440ab0SStefan Agner MX7D_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 62ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_BCLK__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 63ae440ab0SStefan Agner MX7D_PAD_SAI2_TX_SYNC__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 64ae440ab0SStefan Agner }; 65ae440ab0SStefan Agner 66ae440ab0SStefan Agner static iomux_v3_cfg_t const usdhc1_pads[] = { 67ae440ab0SStefan Agner MX7D_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 68ae440ab0SStefan Agner MX7D_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 69ae440ab0SStefan Agner MX7D_PAD_SD1_DATA0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 70ae440ab0SStefan Agner MX7D_PAD_SD1_DATA1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 71ae440ab0SStefan Agner MX7D_PAD_SD1_DATA2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 72ae440ab0SStefan Agner MX7D_PAD_SD1_DATA3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 73ae440ab0SStefan Agner 74ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), 75ae440ab0SStefan Agner }; 76ae440ab0SStefan Agner 775a986dfeSStefan Agner #ifdef CONFIG_USB_EHCI_MX7 785a986dfeSStefan Agner static iomux_v3_cfg_t const usb_cdet_pads[] = { 795a986dfeSStefan Agner MX7D_PAD_ENET1_CRS__GPIO7_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), 805a986dfeSStefan Agner }; 815a986dfeSStefan Agner #endif 825a986dfeSStefan Agner 83ae440ab0SStefan Agner #ifdef CONFIG_NAND_MXS 84ae440ab0SStefan Agner static iomux_v3_cfg_t const gpmi_pads[] = { 85ae440ab0SStefan Agner MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 86ae440ab0SStefan Agner MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 87ae440ab0SStefan Agner MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 88ae440ab0SStefan Agner MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 89ae440ab0SStefan Agner MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 90ae440ab0SStefan Agner MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 91ae440ab0SStefan Agner MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 92ae440ab0SStefan Agner MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 93ae440ab0SStefan Agner MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 94ae440ab0SStefan Agner MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 95ae440ab0SStefan Agner MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 96ae440ab0SStefan Agner MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 97ae440ab0SStefan Agner MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 98ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 99ae440ab0SStefan Agner MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 100ae440ab0SStefan Agner }; 101ae440ab0SStefan Agner 102ae440ab0SStefan Agner static void setup_gpmi_nand(void) 103ae440ab0SStefan Agner { 104ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 105ae440ab0SStefan Agner 106ae440ab0SStefan Agner /* NAND_USDHC_BUS_CLK is set in rom */ 107ae440ab0SStefan Agner set_clk_nand(); 108ae440ab0SStefan Agner } 109ae440ab0SStefan Agner #endif 110ae440ab0SStefan Agner 111ae440ab0SStefan Agner static iomux_v3_cfg_t const usdhc3_emmc_pads[] = { 112ae440ab0SStefan Agner MX7D_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 113ae440ab0SStefan Agner MX7D_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 114ae440ab0SStefan Agner MX7D_PAD_SD3_DATA0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 115ae440ab0SStefan Agner MX7D_PAD_SD3_DATA1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 116ae440ab0SStefan Agner MX7D_PAD_SD3_DATA2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 117ae440ab0SStefan Agner MX7D_PAD_SD3_DATA3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 118ae440ab0SStefan Agner MX7D_PAD_SD3_DATA4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 119ae440ab0SStefan Agner MX7D_PAD_SD3_DATA5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 120ae440ab0SStefan Agner MX7D_PAD_SD3_DATA6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 121ae440ab0SStefan Agner MX7D_PAD_SD3_DATA7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 122ae440ab0SStefan Agner MX7D_PAD_SD3_STROBE__SD3_STROBE | MUX_PAD_CTRL(USDHC_PAD_CTRL), 123ae440ab0SStefan Agner 124ae440ab0SStefan Agner MX7D_PAD_SD3_RESET_B__GPIO6_IO11 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 125ae440ab0SStefan Agner }; 126ae440ab0SStefan Agner 127ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 128ae440ab0SStefan Agner static iomux_v3_cfg_t const lcd_pads[] = { 129ae440ab0SStefan Agner MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 130ae440ab0SStefan Agner MX7D_PAD_LCD_ENABLE__LCD_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 131ae440ab0SStefan Agner MX7D_PAD_LCD_HSYNC__LCD_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 132ae440ab0SStefan Agner MX7D_PAD_LCD_VSYNC__LCD_VSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 133ae440ab0SStefan Agner MX7D_PAD_LCD_DATA00__LCD_DATA0 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134ae440ab0SStefan Agner MX7D_PAD_LCD_DATA01__LCD_DATA1 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135ae440ab0SStefan Agner MX7D_PAD_LCD_DATA02__LCD_DATA2 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136ae440ab0SStefan Agner MX7D_PAD_LCD_DATA03__LCD_DATA3 | MUX_PAD_CTRL(LCD_PAD_CTRL), 137ae440ab0SStefan Agner MX7D_PAD_LCD_DATA04__LCD_DATA4 | MUX_PAD_CTRL(LCD_PAD_CTRL), 138ae440ab0SStefan Agner MX7D_PAD_LCD_DATA05__LCD_DATA5 | MUX_PAD_CTRL(LCD_PAD_CTRL), 139ae440ab0SStefan Agner MX7D_PAD_LCD_DATA06__LCD_DATA6 | MUX_PAD_CTRL(LCD_PAD_CTRL), 140ae440ab0SStefan Agner MX7D_PAD_LCD_DATA07__LCD_DATA7 | MUX_PAD_CTRL(LCD_PAD_CTRL), 141ae440ab0SStefan Agner MX7D_PAD_LCD_DATA08__LCD_DATA8 | MUX_PAD_CTRL(LCD_PAD_CTRL), 142ae440ab0SStefan Agner MX7D_PAD_LCD_DATA09__LCD_DATA9 | MUX_PAD_CTRL(LCD_PAD_CTRL), 143ae440ab0SStefan Agner MX7D_PAD_LCD_DATA10__LCD_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 144ae440ab0SStefan Agner MX7D_PAD_LCD_DATA11__LCD_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 145ae440ab0SStefan Agner MX7D_PAD_LCD_DATA12__LCD_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 146ae440ab0SStefan Agner MX7D_PAD_LCD_DATA13__LCD_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 147ae440ab0SStefan Agner MX7D_PAD_LCD_DATA14__LCD_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 148ae440ab0SStefan Agner MX7D_PAD_LCD_DATA15__LCD_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 149ae440ab0SStefan Agner MX7D_PAD_LCD_DATA16__LCD_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 150ae440ab0SStefan Agner MX7D_PAD_LCD_DATA17__LCD_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 151ae440ab0SStefan Agner }; 152ae440ab0SStefan Agner 153ae440ab0SStefan Agner static iomux_v3_cfg_t const backlight_pads[] = { 154ae440ab0SStefan Agner /* Backlight On */ 155ae440ab0SStefan Agner MX7D_PAD_SD1_WP__GPIO5_IO1 | MUX_PAD_CTRL(NO_PAD_CTRL), 156ae440ab0SStefan Agner /* Backlight PWM<A> (multiplexed pin) */ 157ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(NO_PAD_CTRL), 158ae440ab0SStefan Agner MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 | MUX_PAD_CTRL(NO_PAD_CTRL), 159ae440ab0SStefan Agner }; 160ae440ab0SStefan Agner 161ae440ab0SStefan Agner #define GPIO_BL_ON IMX_GPIO_NR(5, 1) 162ae440ab0SStefan Agner #define GPIO_PWM_A IMX_GPIO_NR(1, 8) 163ae440ab0SStefan Agner 164ae440ab0SStefan Agner static int setup_lcd(void) 165ae440ab0SStefan Agner { 166ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 167ae440ab0SStefan Agner 168ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); 169ae440ab0SStefan Agner 170ae440ab0SStefan Agner /* Set BL_ON */ 171ae440ab0SStefan Agner gpio_request(GPIO_BL_ON, "BL_ON"); 172ae440ab0SStefan Agner gpio_direction_output(GPIO_BL_ON, 1); 173ae440ab0SStefan Agner 174ae440ab0SStefan Agner /* Set PWM<A> to full brightness (assuming inversed polarity) */ 175ae440ab0SStefan Agner gpio_request(GPIO_PWM_A, "PWM<A>"); 176ae440ab0SStefan Agner gpio_direction_output(GPIO_PWM_A, 0); 177ae440ab0SStefan Agner 178ae440ab0SStefan Agner return 0; 179ae440ab0SStefan Agner } 180ae440ab0SStefan Agner #endif 181ae440ab0SStefan Agner 182ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 183ae440ab0SStefan Agner static iomux_v3_cfg_t const fec1_pads[] = { 184ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 185ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, 186ae440ab0SStefan Agner #else 187ae440ab0SStefan Agner MX7D_PAD_GPIO1_IO12__CCM_ENET_REF_CLK1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 188ae440ab0SStefan Agner #endif 189ae440ab0SStefan Agner MX7D_PAD_SD2_CD_B__ENET1_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 190ae440ab0SStefan Agner MX7D_PAD_SD2_WP__ENET1_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 191ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 192ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 193ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RXC__ENET1_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 194ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 195ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), 196ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), 197ae440ab0SStefan Agner MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), 198ae440ab0SStefan Agner }; 199ae440ab0SStefan Agner 200ae440ab0SStefan Agner static void setup_iomux_fec(void) 201ae440ab0SStefan Agner { 202ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); 203ae440ab0SStefan Agner } 204ae440ab0SStefan Agner #endif 205ae440ab0SStefan Agner 206ae440ab0SStefan Agner static void setup_iomux_uart(void) 207ae440ab0SStefan Agner { 208ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 209ae440ab0SStefan Agner } 210ae440ab0SStefan Agner 211ae440ab0SStefan Agner #ifdef CONFIG_FSL_ESDHC 212ae440ab0SStefan Agner 213ae440ab0SStefan Agner #define USDHC1_CD_GPIO IMX_GPIO_NR(1, 0) 214ae440ab0SStefan Agner 215ae440ab0SStefan Agner static struct fsl_esdhc_cfg usdhc_cfg[] = { 216ae440ab0SStefan Agner {USDHC1_BASE_ADDR, 0, 4}, 217ae440ab0SStefan Agner }; 218ae440ab0SStefan Agner 219ae440ab0SStefan Agner int board_mmc_getcd(struct mmc *mmc) 220ae440ab0SStefan Agner { 221ae440ab0SStefan Agner struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 222ae440ab0SStefan Agner int ret = 0; 223ae440ab0SStefan Agner 224ae440ab0SStefan Agner switch (cfg->esdhc_base) { 225ae440ab0SStefan Agner case USDHC1_BASE_ADDR: 226ae440ab0SStefan Agner ret = !gpio_get_value(USDHC1_CD_GPIO); 227ae440ab0SStefan Agner break; 228ae440ab0SStefan Agner } 229ae440ab0SStefan Agner 230ae440ab0SStefan Agner return ret; 231ae440ab0SStefan Agner } 232ae440ab0SStefan Agner 233ae440ab0SStefan Agner int board_mmc_init(bd_t *bis) 234ae440ab0SStefan Agner { 235ae440ab0SStefan Agner int i, ret; 236ae440ab0SStefan Agner /* USDHC1 is mmc0 */ 237ae440ab0SStefan Agner for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 238ae440ab0SStefan Agner switch (i) { 239ae440ab0SStefan Agner case 0: 240ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads( 241ae440ab0SStefan Agner usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); 242ae440ab0SStefan Agner gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 243ae440ab0SStefan Agner gpio_direction_input(USDHC1_CD_GPIO); 244ae440ab0SStefan Agner usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 245ae440ab0SStefan Agner break; 246ae440ab0SStefan Agner default: 247ae440ab0SStefan Agner printf("Warning: you configured more USDHC controllers" 248ae440ab0SStefan Agner "(%d) than supported by the board\n", i + 1); 249ae440ab0SStefan Agner return -EINVAL; 250ae440ab0SStefan Agner } 251ae440ab0SStefan Agner 252ae440ab0SStefan Agner ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 253ae440ab0SStefan Agner if (ret) 254ae440ab0SStefan Agner return ret; 255ae440ab0SStefan Agner } 256ae440ab0SStefan Agner 257ae440ab0SStefan Agner return 0; 258ae440ab0SStefan Agner } 259ae440ab0SStefan Agner #endif 260ae440ab0SStefan Agner 261ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 262ae440ab0SStefan Agner int board_eth_init(bd_t *bis) 263ae440ab0SStefan Agner { 264ae440ab0SStefan Agner int ret; 265ae440ab0SStefan Agner 266ae440ab0SStefan Agner setup_iomux_fec(); 267ae440ab0SStefan Agner 268ae440ab0SStefan Agner ret = fecmxc_initialize_multi(bis, 0, 269ae440ab0SStefan Agner CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE); 270ae440ab0SStefan Agner if (ret) 271ae440ab0SStefan Agner printf("FEC1 MXC: %s:failed\n", __func__); 272ae440ab0SStefan Agner 273ae440ab0SStefan Agner return ret; 274ae440ab0SStefan Agner } 275ae440ab0SStefan Agner 276ae440ab0SStefan Agner static int setup_fec(void) 277ae440ab0SStefan Agner { 278ae440ab0SStefan Agner struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs 279ae440ab0SStefan Agner = (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; 280ae440ab0SStefan Agner 281ae440ab0SStefan Agner #ifndef CONFIG_COLIBRI_IMX7_EXT_PHYCLK 282ae440ab0SStefan Agner /* 283ae440ab0SStefan Agner * Use 50M anatop REF_CLK1 for ENET1, clear gpr1[13], set gpr1[17] 284ae440ab0SStefan Agner * and output it on the pin 285ae440ab0SStefan Agner */ 286ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 287ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK, 288ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK); 289ae440ab0SStefan Agner #else 290ae440ab0SStefan Agner /* Use 50M external CLK for ENET1, set gpr1[13], clear gpr1[17] */ 291ae440ab0SStefan Agner clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], 292ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 293ae440ab0SStefan Agner IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK); 294ae440ab0SStefan Agner #endif 295ae440ab0SStefan Agner 296ae440ab0SStefan Agner return set_clk_enet(ENET_50MHz); 297ae440ab0SStefan Agner } 298ae440ab0SStefan Agner 299ae440ab0SStefan Agner int board_phy_config(struct phy_device *phydev) 300ae440ab0SStefan Agner { 301ae440ab0SStefan Agner if (phydev->drv->config) 302ae440ab0SStefan Agner phydev->drv->config(phydev); 303ae440ab0SStefan Agner return 0; 304ae440ab0SStefan Agner } 305ae440ab0SStefan Agner #endif 306ae440ab0SStefan Agner 307ae440ab0SStefan Agner int board_early_init_f(void) 308ae440ab0SStefan Agner { 309ae440ab0SStefan Agner setup_iomux_uart(); 310ae440ab0SStefan Agner 311ae440ab0SStefan Agner return 0; 312ae440ab0SStefan Agner } 313ae440ab0SStefan Agner 314ae440ab0SStefan Agner int board_init(void) 315ae440ab0SStefan Agner { 316ae440ab0SStefan Agner /* address of boot parameters */ 317ae440ab0SStefan Agner gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 318ae440ab0SStefan Agner 319ae440ab0SStefan Agner #ifdef CONFIG_FEC_MXC 320ae440ab0SStefan Agner setup_fec(); 321ae440ab0SStefan Agner #endif 322ae440ab0SStefan Agner 323ae440ab0SStefan Agner #ifdef CONFIG_NAND_MXS 324ae440ab0SStefan Agner setup_gpmi_nand(); 325ae440ab0SStefan Agner #endif 326ae440ab0SStefan Agner 327ae440ab0SStefan Agner #ifdef CONFIG_VIDEO_MXS 328ae440ab0SStefan Agner setup_lcd(); 329ae440ab0SStefan Agner #endif 330ae440ab0SStefan Agner 3315a986dfeSStefan Agner #ifdef CONFIG_USB_EHCI_MX7 3325a986dfeSStefan Agner imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); 3335a986dfeSStefan Agner gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); 3345a986dfeSStefan Agner #endif 3355a986dfeSStefan Agner 336ae440ab0SStefan Agner return 0; 337ae440ab0SStefan Agner } 338ae440ab0SStefan Agner 339ae440ab0SStefan Agner #ifdef CONFIG_CMD_BMODE 340ae440ab0SStefan Agner static const struct boot_mode board_boot_modes[] = { 341ae440ab0SStefan Agner /* 4 bit bus width */ 342ae440ab0SStefan Agner {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, 343ae440ab0SStefan Agner {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 344ae440ab0SStefan Agner {NULL, 0}, 345ae440ab0SStefan Agner }; 346ae440ab0SStefan Agner #endif 347ae440ab0SStefan Agner 348ae440ab0SStefan Agner int board_late_init(void) 349ae440ab0SStefan Agner { 350ae440ab0SStefan Agner #ifdef CONFIG_CMD_BMODE 351ae440ab0SStefan Agner add_board_boot_modes(board_boot_modes); 352ae440ab0SStefan Agner #endif 353ae440ab0SStefan Agner 354ae440ab0SStefan Agner return 0; 355ae440ab0SStefan Agner } 356ae440ab0SStefan Agner 35702ad90ecSStefan Agner #ifdef CONFIG_DM_PMIC 35802ad90ecSStefan Agner int power_init_board(void) 35902ad90ecSStefan Agner { 36002ad90ecSStefan Agner struct udevice *dev; 36102ad90ecSStefan Agner int reg, ver; 36202ad90ecSStefan Agner int ret; 36302ad90ecSStefan Agner 36402ad90ecSStefan Agner 36502ad90ecSStefan Agner ret = pmic_get("rn5t567", &dev); 36602ad90ecSStefan Agner if (ret) 36702ad90ecSStefan Agner return ret; 36802ad90ecSStefan Agner ver = pmic_reg_read(dev, RN5T567_LSIVER); 36902ad90ecSStefan Agner reg = pmic_reg_read(dev, RN5T567_OTPVER); 37002ad90ecSStefan Agner 37102ad90ecSStefan Agner printf("PMIC: RN5T567 LSIVER=0x%02x OTPVER=0x%02x\n", ver, reg); 37202ad90ecSStefan Agner 37302ad90ecSStefan Agner /* set judge and press timer of N_OE to minimal values */ 37402ad90ecSStefan Agner pmic_clrsetbits(dev, RN5T567_NOETIMSETCNT, 0x7, 0); 37502ad90ecSStefan Agner 376*05ed964dSStefan Agner /* configure sleep slot for 3.3V Ethernet */ 377*05ed964dSStefan Agner reg = pmic_reg_read(dev, RN5T567_LDO1_SLOT); 378*05ed964dSStefan Agner reg = (reg & 0xf0) | reg >> 4; 379*05ed964dSStefan Agner pmic_reg_write(dev, RN5T567_LDO1_SLOT, reg); 380*05ed964dSStefan Agner 381*05ed964dSStefan Agner /* disable DCDC2 discharge to avoid backfeeding through VFB2 */ 382*05ed964dSStefan Agner pmic_clrsetbits(dev, RN5T567_DC2CTL, 0x2, 0); 383*05ed964dSStefan Agner 384*05ed964dSStefan Agner /* configure sleep slot for ARM rail */ 385*05ed964dSStefan Agner reg = pmic_reg_read(dev, RN5T567_DC2_SLOT); 386*05ed964dSStefan Agner reg = (reg & 0xf0) | reg >> 4; 387*05ed964dSStefan Agner pmic_reg_write(dev, RN5T567_DC2_SLOT, reg); 388*05ed964dSStefan Agner 389*05ed964dSStefan Agner /* disable LDO2 discharge to avoid backfeeding from +V3.3_SD */ 390*05ed964dSStefan Agner pmic_clrsetbits(dev, RN5T567_LDODIS1, 0x2, 0); 391*05ed964dSStefan Agner 39202ad90ecSStefan Agner return 0; 39302ad90ecSStefan Agner } 39402ad90ecSStefan Agner 39502ad90ecSStefan Agner void reset_cpu(ulong addr) 39602ad90ecSStefan Agner { 39702ad90ecSStefan Agner struct udevice *dev; 39802ad90ecSStefan Agner 39902ad90ecSStefan Agner pmic_get("rn5t567", &dev); 40002ad90ecSStefan Agner 40102ad90ecSStefan Agner /* Use PMIC to reset, set REPWRTIM to 0 and REPWRON to 1 */ 40202ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_REPCNT, 0x1); 40302ad90ecSStefan Agner pmic_reg_write(dev, RN5T567_SLPCNT, 0x1); 40402ad90ecSStefan Agner 40502ad90ecSStefan Agner /* 40602ad90ecSStefan Agner * Re-power factor detection on PMIC side is not instant. 1ms 40702ad90ecSStefan Agner * proved to be enough time until reset takes effect. 40802ad90ecSStefan Agner */ 40902ad90ecSStefan Agner mdelay(1); 41002ad90ecSStefan Agner } 41102ad90ecSStefan Agner #endif 41202ad90ecSStefan Agner 413ae440ab0SStefan Agner int checkboard(void) 414ae440ab0SStefan Agner { 415ae440ab0SStefan Agner printf("Model: Toradex Colibri iMX7%c\n", 416ae440ab0SStefan Agner is_cpu_type(MXC_CPU_MX7D) ? 'D' : 'S'); 417ae440ab0SStefan Agner 418ae440ab0SStefan Agner return 0; 419ae440ab0SStefan Agner } 420ae440ab0SStefan Agner 42137fa4125SStefan Agner #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 42237fa4125SStefan Agner int ft_board_setup(void *blob, bd_t *bd) 42337fa4125SStefan Agner { 42437fa4125SStefan Agner return ft_common_board_setup(blob, bd); 42537fa4125SStefan Agner } 42637fa4125SStefan Agner #endif 42737fa4125SStefan Agner 428ae440ab0SStefan Agner #ifdef CONFIG_USB_EHCI_MX7 429ae440ab0SStefan Agner static iomux_v3_cfg_t const usb_otg2_pads[] = { 430ae440ab0SStefan Agner MX7D_PAD_UART3_CTS_B__USB_OTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), 431ae440ab0SStefan Agner }; 432ae440ab0SStefan Agner 433ae440ab0SStefan Agner int board_ehci_hcd_init(int port) 434ae440ab0SStefan Agner { 435ae440ab0SStefan Agner switch (port) { 436ae440ab0SStefan Agner case 0: 437ae440ab0SStefan Agner break; 438ae440ab0SStefan Agner case 1: 439ae440ab0SStefan Agner if (is_cpu_type(MXC_CPU_MX7S)) 440ae440ab0SStefan Agner return -ENODEV; 441ae440ab0SStefan Agner 442ae440ab0SStefan Agner imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 443ae440ab0SStefan Agner ARRAY_SIZE(usb_otg2_pads)); 444ae440ab0SStefan Agner break; 445ae440ab0SStefan Agner default: 446ae440ab0SStefan Agner return -EINVAL; 447ae440ab0SStefan Agner } 448ae440ab0SStefan Agner return 0; 449ae440ab0SStefan Agner } 4505a986dfeSStefan Agner 4515a986dfeSStefan Agner int board_usb_phy_mode(int port) 4525a986dfeSStefan Agner { 4535a986dfeSStefan Agner switch (port) { 4545a986dfeSStefan Agner case 0: 4555a986dfeSStefan Agner if (gpio_get_value(USB_CDET_GPIO)) 4565a986dfeSStefan Agner return USB_INIT_DEVICE; 4575a986dfeSStefan Agner else 4585a986dfeSStefan Agner return USB_INIT_HOST; 4595a986dfeSStefan Agner case 1: 4605a986dfeSStefan Agner default: 4615a986dfeSStefan Agner return USB_INIT_HOST; 4625a986dfeSStefan Agner } 4635a986dfeSStefan Agner } 464ae440ab0SStefan Agner #endif 465