1 /*
2  * Copyright (C) 2010-2013 Freescale Semiconductor, Inc.
3  * Copyright (C) 2013, Boundary Devices <info@boundarydevices.com>
4  * Copyright (C) 2014-2016, Toradex AG
5  * copied from nitrogen6x
6  *
7  * SPDX-License-Identifier:	GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <dm.h>
12 #include <asm/arch/clock.h>
13 #include <asm/arch/crm_regs.h>
14 #include <asm/arch/imx-regs.h>
15 #include <asm/arch/iomux.h>
16 #include <asm/arch/mx6-pins.h>
17 #include <asm/arch/mx6-ddr.h>
18 #include <asm/arch/mxc_hdmi.h>
19 #include <asm/arch/sys_proto.h>
20 #include <asm/bootm.h>
21 #include <asm/gpio.h>
22 #include <asm/mach-imx/iomux-v3.h>
23 #include <asm/mach-imx/mxc_i2c.h>
24 #include <asm/mach-imx/sata.h>
25 #include <asm/mach-imx/boot_mode.h>
26 #include <asm/mach-imx/video.h>
27 #include <asm/io.h>
28 #include <dm/platform_data/serial_mxc.h>
29 #include <dm/platdata.h>
30 #include <fsl_esdhc.h>
31 #include <i2c.h>
32 #include <imx_thermal.h>
33 #include <linux/errno.h>
34 #include <malloc.h>
35 #include <micrel.h>
36 #include <miiphy.h>
37 #include <mmc.h>
38 #include <netdev.h>
39 
40 #include "../common/tdx-cfg-block.h"
41 #ifdef CONFIG_TDX_CMD_IMX_MFGR
42 #include "pf0100.h"
43 #endif
44 
45 DECLARE_GLOBAL_DATA_PTR;
46 
47 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
48 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
49 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
50 
51 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
52 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
53 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
54 
55 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
56 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
57 
58 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED |		\
59 	PAD_CTL_DSE_40ohm     | PAD_CTL_SRE_FAST)
60 
61 #define BUTTON_PAD_CTRL (PAD_CTL_PUS_100K_UP |			\
62 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
63 
64 #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
65 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
66 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
67 
68 #define WEAK_PULLUP	(PAD_CTL_PUS_100K_UP |			\
69 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
70 	PAD_CTL_SRE_SLOW)
71 
72 #define NO_PULLUP	(					\
73 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
74 	PAD_CTL_SRE_SLOW)
75 
76 #define WEAK_PULLDOWN	(PAD_CTL_PUS_100K_DOWN |		\
77 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
78 	PAD_CTL_HYS | PAD_CTL_SRE_SLOW)
79 
80 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
81 
82 #define OUTPUT_RGB (PAD_CTL_SPEED_MED|PAD_CTL_DSE_60ohm|PAD_CTL_SRE_FAST)
83 
84 int dram_init(void)
85 {
86 	/* use the DDR controllers configured size */
87 	gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
88 				    (ulong)imx_ddr_size());
89 
90 	return 0;
91 }
92 
93 /* Colibri UARTA */
94 iomux_v3_cfg_t const uart1_pads[] = {
95 	MX6_PAD_CSI0_DAT10__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
96 	MX6_PAD_CSI0_DAT11__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
97 };
98 
99 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
100 /* Colibri I2C */
101 struct i2c_pads_info i2c_pad_info1 = {
102 	.scl = {
103 		.i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC,
104 		.gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC,
105 		.gp = IMX_GPIO_NR(1, 3)
106 	},
107 	.sda = {
108 		.i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC,
109 		.gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC,
110 		.gp = IMX_GPIO_NR(1, 6)
111 	}
112 };
113 
114 /* Colibri local, PMIC, SGTL5000, STMPE811 */
115 struct i2c_pads_info i2c_pad_info_loc = {
116 	.scl = {
117 		.i2c_mode = MX6_PAD_EIM_EB2__I2C2_SCL | PC,
118 		.gpio_mode = MX6_PAD_EIM_EB2__GPIO2_IO30 | PC,
119 		.gp = IMX_GPIO_NR(2, 30)
120 	},
121 	.sda = {
122 		.i2c_mode = MX6_PAD_EIM_D16__I2C2_SDA | PC,
123 		.gpio_mode = MX6_PAD_EIM_D16__GPIO3_IO16 | PC,
124 		.gp = IMX_GPIO_NR(3, 16)
125 	}
126 };
127 
128 /* Apalis MMC */
129 iomux_v3_cfg_t const usdhc1_pads[] = {
130 	MX6_PAD_SD1_CLK__SD1_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
131 	MX6_PAD_SD1_CMD__SD1_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
132 	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
133 	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
134 	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
135 	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
136 	MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
137 #	define GPIO_MMC_CD IMX_GPIO_NR(2, 5)
138 };
139 
140 /* eMMC */
141 iomux_v3_cfg_t const usdhc3_pads[] = {
142 	MX6_PAD_SD3_CLK__SD3_CLK    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
143 	MX6_PAD_SD3_CMD__SD3_CMD    | MUX_PAD_CTRL(USDHC_PAD_CTRL),
144 	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
145 	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
146 	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
147 	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
148 	MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
149 	MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
150 	MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
151 	MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
152 	MX6_PAD_SD3_RST__SD3_RESET  | MUX_PAD_CTRL(USDHC_PAD_CTRL),
153 };
154 
155 iomux_v3_cfg_t const enet_pads[] = {
156 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
157 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
158 	MX6_PAD_ENET_RXD0__ENET_RX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
159 	MX6_PAD_ENET_RXD1__ENET_RX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
160 	MX6_PAD_ENET_RX_ER__ENET_RX_ER		| MUX_PAD_CTRL(ENET_PAD_CTRL),
161 	MX6_PAD_ENET_TX_EN__ENET_TX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
162 	MX6_PAD_ENET_TXD0__ENET_TX_DATA0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
163 	MX6_PAD_ENET_TXD1__ENET_TX_DATA1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
164 	MX6_PAD_ENET_CRS_DV__ENET_RX_EN		| MUX_PAD_CTRL(ENET_PAD_CTRL),
165 	MX6_PAD_GPIO_16__ENET_REF_CLK		| MUX_PAD_CTRL(ENET_PAD_CTRL),
166 };
167 
168 static void setup_iomux_enet(void)
169 {
170 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
171 }
172 
173 /* mux auxiliary pins to GPIO, so they can be used from the U-Boot cmdline */
174 iomux_v3_cfg_t const gpio_pads[] = {
175 	/* ADDRESS[17:18] [25] used as GPIO */
176 	MX6_PAD_KEY_ROW2__GPIO4_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
177 	MX6_PAD_KEY_COL2__GPIO4_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
178 	MX6_PAD_NANDF_D1__GPIO2_IO01	| MUX_PAD_CTRL(WEAK_PULLUP),
179 	/* ADDRESS[19:24] used as GPIO */
180 	MX6_PAD_DISP0_DAT23__GPIO5_IO17 | MUX_PAD_CTRL(WEAK_PULLUP),
181 	MX6_PAD_DISP0_DAT22__GPIO5_IO16 | MUX_PAD_CTRL(WEAK_PULLUP),
182 	MX6_PAD_DISP0_DAT21__GPIO5_IO15 | MUX_PAD_CTRL(WEAK_PULLUP),
183 	MX6_PAD_DISP0_DAT20__GPIO5_IO14 | MUX_PAD_CTRL(WEAK_PULLUP),
184 	MX6_PAD_DISP0_DAT19__GPIO5_IO13 | MUX_PAD_CTRL(WEAK_PULLUP),
185 	MX6_PAD_DISP0_DAT18__GPIO5_IO12 | MUX_PAD_CTRL(WEAK_PULLUP),
186 	/* DATA[16:29] [31]	 used as GPIO */
187 	MX6_PAD_EIM_LBA__GPIO2_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
188 	MX6_PAD_EIM_BCLK__GPIO6_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
189 	MX6_PAD_NANDF_CS3__GPIO6_IO16	| MUX_PAD_CTRL(WEAK_PULLUP),
190 	MX6_PAD_NANDF_CS1__GPIO6_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
191 	MX6_PAD_NANDF_RB0__GPIO6_IO10	| MUX_PAD_CTRL(WEAK_PULLUP),
192 	MX6_PAD_NANDF_ALE__GPIO6_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
193 	MX6_PAD_NANDF_WP_B__GPIO6_IO09	| MUX_PAD_CTRL(WEAK_PULLUP),
194 	MX6_PAD_NANDF_CS0__GPIO6_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
195 	MX6_PAD_NANDF_CLE__GPIO6_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
196 	MX6_PAD_GPIO_19__GPIO4_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
197 	MX6_PAD_CSI0_MCLK__GPIO5_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
198 	MX6_PAD_CSI0_PIXCLK__GPIO5_IO18 | MUX_PAD_CTRL(WEAK_PULLUP),
199 	MX6_PAD_GPIO_4__GPIO1_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
200 	MX6_PAD_GPIO_5__GPIO1_IO05	| MUX_PAD_CTRL(WEAK_PULLUP),
201 	MX6_PAD_GPIO_2__GPIO1_IO02	| MUX_PAD_CTRL(WEAK_PULLUP),
202 	/* DQM[0:3]	 used as GPIO */
203 	MX6_PAD_EIM_EB0__GPIO2_IO28	| MUX_PAD_CTRL(WEAK_PULLUP),
204 	MX6_PAD_EIM_EB1__GPIO2_IO29	| MUX_PAD_CTRL(WEAK_PULLUP),
205 	MX6_PAD_SD2_DAT2__GPIO1_IO13	| MUX_PAD_CTRL(WEAK_PULLUP),
206 	MX6_PAD_NANDF_D0__GPIO2_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
207 	/* RDY	used as GPIO */
208 	MX6_PAD_EIM_WAIT__GPIO5_IO00	| MUX_PAD_CTRL(WEAK_PULLUP),
209 	/* ADDRESS[16] DATA[30]	 used as GPIO */
210 	MX6_PAD_KEY_ROW4__GPIO4_IO15	| MUX_PAD_CTRL(WEAK_PULLDOWN),
211 	MX6_PAD_KEY_COL4__GPIO4_IO14	| MUX_PAD_CTRL(WEAK_PULLUP),
212 	/* CSI pins used as GPIO */
213 	MX6_PAD_EIM_A24__GPIO5_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
214 	MX6_PAD_SD2_CMD__GPIO1_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
215 	MX6_PAD_NANDF_CS2__GPIO6_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
216 	MX6_PAD_EIM_D18__GPIO3_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
217 	MX6_PAD_EIM_A19__GPIO2_IO19	| MUX_PAD_CTRL(WEAK_PULLUP),
218 	MX6_PAD_EIM_D29__GPIO3_IO29	| MUX_PAD_CTRL(WEAK_PULLDOWN),
219 	MX6_PAD_EIM_A23__GPIO6_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
220 	MX6_PAD_EIM_A20__GPIO2_IO18	| MUX_PAD_CTRL(WEAK_PULLUP),
221 	MX6_PAD_EIM_A17__GPIO2_IO21	| MUX_PAD_CTRL(WEAK_PULLUP),
222 	MX6_PAD_EIM_A18__GPIO2_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
223 	MX6_PAD_EIM_EB3__GPIO2_IO31	| MUX_PAD_CTRL(WEAK_PULLUP),
224 	MX6_PAD_EIM_D17__GPIO3_IO17	| MUX_PAD_CTRL(WEAK_PULLUP),
225 	MX6_PAD_SD2_DAT0__GPIO1_IO15	| MUX_PAD_CTRL(WEAK_PULLUP),
226 	/* GPIO */
227 	MX6_PAD_EIM_D26__GPIO3_IO26	| MUX_PAD_CTRL(WEAK_PULLUP),
228 	MX6_PAD_EIM_D27__GPIO3_IO27	| MUX_PAD_CTRL(WEAK_PULLUP),
229 	MX6_PAD_NANDF_D6__GPIO2_IO06	| MUX_PAD_CTRL(WEAK_PULLUP),
230 	MX6_PAD_NANDF_D3__GPIO2_IO03	| MUX_PAD_CTRL(WEAK_PULLUP),
231 	MX6_PAD_ENET_REF_CLK__GPIO1_IO23 | MUX_PAD_CTRL(WEAK_PULLUP),
232 	MX6_PAD_DI0_PIN4__GPIO4_IO20	| MUX_PAD_CTRL(WEAK_PULLUP),
233 	MX6_PAD_SD4_DAT3__GPIO2_IO11	| MUX_PAD_CTRL(WEAK_PULLUP),
234 	MX6_PAD_NANDF_D4__GPIO2_IO04	| MUX_PAD_CTRL(WEAK_PULLUP),
235 	MX6_PAD_SD4_DAT0__GPIO2_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
236 	MX6_PAD_GPIO_7__GPIO1_IO07	| MUX_PAD_CTRL(WEAK_PULLUP),
237 	MX6_PAD_GPIO_8__GPIO1_IO08	| MUX_PAD_CTRL(WEAK_PULLUP),
238 	/* USBH_OC */
239 	MX6_PAD_EIM_D30__GPIO3_IO30	| MUX_PAD_CTRL(WEAK_PULLUP),
240 	/* USBC_ID */
241 	MX6_PAD_NANDF_D2__GPIO2_IO02	| MUX_PAD_CTRL(WEAK_PULLUP),
242 	/* USBC_DET */
243 	MX6_PAD_GPIO_17__GPIO7_IO12	| MUX_PAD_CTRL(WEAK_PULLUP),
244 };
245 
246 static void setup_iomux_gpio(void)
247 {
248 	imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads));
249 }
250 
251 iomux_v3_cfg_t const usb_pads[] = {
252 	/* USB_PE */
253 	MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL),
254 #	define GPIO_USBH_EN IMX_GPIO_NR(3, 31)
255 };
256 
257 /*
258  * UARTs are used in DTE mode, switch the mode on all UARTs before
259  * any pinmuxing connects a (DCE) output to a transceiver output.
260  */
261 #define UFCR		0x90	/* FIFO Control Register */
262 #define UFCR_DCEDTE	(1<<6)	/* DCE=0 */
263 
264 static void setup_dtemode_uart(void)
265 {
266 	setbits_le32((u32 *)(UART1_BASE + UFCR), UFCR_DCEDTE);
267 	setbits_le32((u32 *)(UART2_BASE + UFCR), UFCR_DCEDTE);
268 	setbits_le32((u32 *)(UART3_BASE + UFCR), UFCR_DCEDTE);
269 }
270 
271 static void setup_iomux_uart(void)
272 {
273 	setup_dtemode_uart();
274 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
275 }
276 
277 #ifdef CONFIG_USB_EHCI_MX6
278 int board_ehci_hcd_init(int port)
279 {
280 	imx_iomux_v3_setup_multiple_pads(usb_pads, ARRAY_SIZE(usb_pads));
281 	return 0;
282 }
283 
284 int board_ehci_power(int port, int on)
285 {
286 	switch (port) {
287 	case 0:
288 		/* control OTG power */
289 		/* No special PE for USBC, always on when ID pin signals
290 		   host mode */
291 		break;
292 	case 1:
293 		/* Control MXM USBH */
294 		/* Set MXM USBH power enable, '0' means on */
295 		gpio_direction_output(GPIO_USBH_EN, !on);
296 		mdelay(100);
297 		break;
298 	default:
299 		break;
300 	}
301 	return 0;
302 }
303 #endif
304 
305 #ifdef CONFIG_FSL_ESDHC
306 /* use the following sequence: eMMC, MMC */
307 struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
308 	{USDHC3_BASE_ADDR},
309 	{USDHC1_BASE_ADDR},
310 };
311 
312 int board_mmc_getcd(struct mmc *mmc)
313 {
314 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
315 	int ret = true; /* default: assume inserted */
316 
317 	switch (cfg->esdhc_base) {
318 	case USDHC1_BASE_ADDR:
319 		gpio_direction_input(GPIO_MMC_CD);
320 		ret = !gpio_get_value(GPIO_MMC_CD);
321 		break;
322 	}
323 
324 	return ret;
325 }
326 
327 int board_mmc_init(bd_t *bis)
328 {
329 #ifndef CONFIG_SPL_BUILD
330 	s32 status = 0;
331 	u32 index = 0;
332 
333 	usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
334 	usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
335 
336 	usdhc_cfg[0].max_bus_width = 8;
337 	usdhc_cfg[1].max_bus_width = 4;
338 
339 	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
340 		switch (index) {
341 		case 0:
342 			imx_iomux_v3_setup_multiple_pads(
343 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
344 			break;
345 		case 1:
346 			imx_iomux_v3_setup_multiple_pads(
347 				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
348 			break;
349 		default:
350 			printf("Warning: you configured more USDHC controllers (%d) then supported by the board (%d)\n",
351 			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);
352 			return status;
353 		}
354 
355 		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
356 	}
357 
358 	return status;
359 #else
360 	struct src *psrc = (struct src *)SRC_BASE_ADDR;
361 	unsigned reg = readl(&psrc->sbmr1) >> 11;
362 	/*
363 	 * Upon reading BOOT_CFG register the following map is done:
364 	 * Bit 11 and 12 of BOOT_CFG register can determine the current
365 	 * mmc port
366 	 * 0x1                  SD1
367 	 * 0x2                  SD2
368 	 * 0x3                  SD4
369 	 */
370 
371 	switch (reg & 0x3) {
372 	case 0x0:
373 		imx_iomux_v3_setup_multiple_pads(
374 			usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
375 		usdhc_cfg[0].esdhc_base = USDHC1_BASE_ADDR;
376 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
377 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
378 		break;
379 	case 0x2:
380 		imx_iomux_v3_setup_multiple_pads(
381 			usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
382 		usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR;
383 		usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
384 		gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk;
385 		break;
386 	default:
387 		puts("MMC boot device not available");
388 	}
389 
390 	return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
391 #endif
392 }
393 #endif
394 
395 int board_phy_config(struct phy_device *phydev)
396 {
397 	if (phydev->drv->config)
398 		phydev->drv->config(phydev);
399 
400 	return 0;
401 }
402 
403 int board_eth_init(bd_t *bis)
404 {
405 	struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
406 	uint32_t base = IMX_FEC_BASE;
407 	struct mii_dev *bus = NULL;
408 	struct phy_device *phydev = NULL;
409 	int ret;
410 
411 	/* provide the PHY clock from the i.MX 6 */
412 	ret = enable_fec_anatop_clock(0, ENET_50MHZ);
413 	if (ret)
414 		return ret;
415 	/* set gpr1[ENET_CLK_SEL] */
416 	setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK);
417 
418 	setup_iomux_enet();
419 
420 #ifdef CONFIG_FEC_MXC
421 	bus = fec_get_miibus(base, -1);
422 	if (!bus)
423 		return 0;
424 	/* scan PHY 1..7 */
425 	phydev = phy_find_by_mask(bus, 0xff, PHY_INTERFACE_MODE_RMII);
426 	if (!phydev) {
427 		free(bus);
428 		puts("no PHY found\n");
429 		return 0;
430 	}
431 	phy_reset(phydev);
432 	printf("using PHY at %d\n", phydev->addr);
433 	ret = fec_probe(bis, -1, base, bus, phydev);
434 	if (ret) {
435 		printf("FEC MXC: %s:failed\n", __func__);
436 		free(phydev);
437 		free(bus);
438 	}
439 #endif
440 	return 0;
441 }
442 
443 static iomux_v3_cfg_t const pwr_intb_pads[] = {
444 	/*
445 	 * the bootrom sets the iomux to vselect, potentially connecting
446 	 * two outputs. Set this back to GPIO
447 	 */
448 	MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL)
449 };
450 
451 #if defined(CONFIG_VIDEO_IPUV3)
452 
453 static iomux_v3_cfg_t const backlight_pads[] = {
454 	/* Backlight On */
455 	MX6_PAD_EIM_D26__GPIO3_IO26 | MUX_PAD_CTRL(NO_PAD_CTRL),
456 #define RGB_BACKLIGHT_GP IMX_GPIO_NR(3, 26)
457 	/* Backlight PWM, used as GPIO in U-Boot */
458 	MX6_PAD_EIM_A22__GPIO2_IO16  | MUX_PAD_CTRL(NO_PULLUP),
459 	MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL),
460 #define RGB_BACKLIGHTPWM_GP IMX_GPIO_NR(2, 9)
461 };
462 
463 static iomux_v3_cfg_t const rgb_pads[] = {
464 	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(OUTPUT_RGB),
465 	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(OUTPUT_RGB),
466 	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(OUTPUT_RGB),
467 	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(OUTPUT_RGB),
468 	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(OUTPUT_RGB),
469 	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(OUTPUT_RGB),
470 	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(OUTPUT_RGB),
471 	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(OUTPUT_RGB),
472 	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(OUTPUT_RGB),
473 	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(OUTPUT_RGB),
474 	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(OUTPUT_RGB),
475 	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(OUTPUT_RGB),
476 	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(OUTPUT_RGB),
477 	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(OUTPUT_RGB),
478 	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(OUTPUT_RGB),
479 	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(OUTPUT_RGB),
480 	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(OUTPUT_RGB),
481 	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(OUTPUT_RGB),
482 	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(OUTPUT_RGB),
483 	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(OUTPUT_RGB),
484 	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(OUTPUT_RGB),
485 	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(OUTPUT_RGB),
486 };
487 
488 static void do_enable_hdmi(struct display_info_t const *dev)
489 {
490 	imx_enable_hdmi_phy();
491 }
492 
493 static void enable_rgb(struct display_info_t const *dev)
494 {
495 	imx_iomux_v3_setup_multiple_pads(
496 		rgb_pads,
497 		ARRAY_SIZE(rgb_pads));
498 	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
499 	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
500 }
501 
502 static int detect_default(struct display_info_t const *dev)
503 {
504 	(void) dev;
505 	return 1;
506 }
507 
508 struct display_info_t const displays[] = {{
509 	.bus	= -1,
510 	.addr	= 0,
511 	.pixfmt	= IPU_PIX_FMT_RGB24,
512 	.detect	= detect_hdmi,
513 	.enable	= do_enable_hdmi,
514 	.mode	= {
515 		.name           = "HDMI",
516 		.refresh        = 60,
517 		.xres           = 1024,
518 		.yres           = 768,
519 		.pixclock       = 15385,
520 		.left_margin    = 220,
521 		.right_margin   = 40,
522 		.upper_margin   = 21,
523 		.lower_margin   = 7,
524 		.hsync_len      = 60,
525 		.vsync_len      = 10,
526 		.sync           = FB_SYNC_EXT,
527 		.vmode          = FB_VMODE_NONINTERLACED
528 } }, {
529 	.bus	= -1,
530 	.addr	= 0,
531 	.pixfmt	= IPU_PIX_FMT_RGB666,
532 	.detect	= detect_default,
533 	.enable	= enable_rgb,
534 	.mode	= {
535 		.name           = "vga-rgb",
536 		.refresh        = 60,
537 		.xres           = 640,
538 		.yres           = 480,
539 		.pixclock       = 33000,
540 		.left_margin    = 48,
541 		.right_margin   = 16,
542 		.upper_margin   = 31,
543 		.lower_margin   = 11,
544 		.hsync_len      = 96,
545 		.vsync_len      = 2,
546 		.sync           = 0,
547 		.vmode          = FB_VMODE_NONINTERLACED
548 } }, {
549 	.bus	= -1,
550 	.addr	= 0,
551 	.pixfmt	= IPU_PIX_FMT_RGB666,
552 	.enable	= enable_rgb,
553 	.mode	= {
554 		.name           = "wvga-rgb",
555 		.refresh        = 60,
556 		.xres           = 800,
557 		.yres           = 480,
558 		.pixclock       = 25000,
559 		.left_margin    = 40,
560 		.right_margin   = 88,
561 		.upper_margin   = 33,
562 		.lower_margin   = 10,
563 		.hsync_len      = 128,
564 		.vsync_len      = 2,
565 		.sync           = 0,
566 		.vmode          = FB_VMODE_NONINTERLACED
567 } } };
568 size_t display_count = ARRAY_SIZE(displays);
569 
570 static void setup_display(void)
571 {
572 	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
573 	struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
574 	int reg;
575 
576 	enable_ipu_clock();
577 	imx_setup_hdmi();
578 	/* Turn on LDB0,IPU,IPU DI0 clocks */
579 	reg = __raw_readl(&mxc_ccm->CCGR3);
580 	reg |= MXC_CCM_CCGR3_LDB_DI0_MASK;
581 	writel(reg, &mxc_ccm->CCGR3);
582 
583 	/* set LDB0, LDB1 clk select to 011/011 */
584 	reg = readl(&mxc_ccm->cs2cdr);
585 	reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
586 		 |MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
587 	reg |= (3<<MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
588 	      |(3<<MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
589 	writel(reg, &mxc_ccm->cs2cdr);
590 
591 	reg = readl(&mxc_ccm->cscmr2);
592 	reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
593 	writel(reg, &mxc_ccm->cscmr2);
594 
595 	reg = readl(&mxc_ccm->chsccdr);
596 	reg |= (CHSCCDR_CLK_SEL_LDB_DI0
597 		<<MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
598 	writel(reg, &mxc_ccm->chsccdr);
599 
600 	reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
601 	     |IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
602 	     |IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
603 	     |IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
604 	     |IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
605 	     |IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
606 	     |IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
607 	     |IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
608 	     |IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
609 	writel(reg, &iomux->gpr[2]);
610 
611 	reg = readl(&iomux->gpr[3]);
612 	reg = (reg & ~(IOMUXC_GPR3_LVDS0_MUX_CTL_MASK
613 			|IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
614 	    | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
615 	       <<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
616 	writel(reg, &iomux->gpr[3]);
617 
618 	/* backlight unconditionally on for now */
619 	imx_iomux_v3_setup_multiple_pads(backlight_pads,
620 					 ARRAY_SIZE(backlight_pads));
621 	/* use 0 for EDT 7", use 1 for LG fullHD panel */
622 	gpio_direction_output(RGB_BACKLIGHTPWM_GP, 0);
623 	gpio_direction_output(RGB_BACKLIGHT_GP, 1);
624 }
625 #endif /* defined(CONFIG_VIDEO_IPUV3) */
626 
627 int board_early_init_f(void)
628 {
629 	imx_iomux_v3_setup_multiple_pads(pwr_intb_pads,
630 					 ARRAY_SIZE(pwr_intb_pads));
631 	setup_iomux_uart();
632 
633 #if defined(CONFIG_VIDEO_IPUV3)
634 	setup_display();
635 #endif
636 	return 0;
637 }
638 
639 /*
640  * Do not overwrite the console
641  * Use always serial for U-Boot console
642  */
643 int overwrite_console(void)
644 {
645 	return 1;
646 }
647 
648 int board_init(void)
649 {
650 	/* address of boot parameters */
651 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
652 
653 	setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
654 	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info_loc);
655 
656 #ifdef CONFIG_TDX_CMD_IMX_MFGR
657 	(void) pmic_init();
658 #endif
659 
660 #ifdef CONFIG_SATA
661 	setup_sata();
662 #endif
663 
664 	setup_iomux_gpio();
665 
666 	return 0;
667 }
668 
669 #ifdef CONFIG_BOARD_LATE_INIT
670 int board_late_init(void)
671 {
672 #if defined(CONFIG_REVISION_TAG) && \
673     defined(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)
674 	char env_str[256];
675 	u32 rev;
676 
677 	rev = get_board_rev();
678 	snprintf(env_str, ARRAY_SIZE(env_str), "%.4x", rev);
679 	env_set("board_rev", env_str);
680 #endif
681 
682 	return 0;
683 }
684 #endif /* CONFIG_BOARD_LATE_INIT */
685 
686 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_SYSTEM_SETUP)
687 int ft_system_setup(void *blob, bd_t *bd)
688 {
689 	return 0;
690 }
691 #endif
692 
693 int checkboard(void)
694 {
695 	char it[] = " IT";
696 	int minc, maxc;
697 
698 	switch (get_cpu_temp_grade(&minc, &maxc)) {
699 	case TEMP_AUTOMOTIVE:
700 	case TEMP_INDUSTRIAL:
701 		break;
702 	case TEMP_EXTCOMMERCIAL:
703 	default:
704 		it[0] = 0;
705 	};
706 	printf("Model: Toradex Colibri iMX6 %s %sMB%s\n",
707 	       is_cpu_type(MXC_CPU_MX6DL) ? "DualLite" : "Solo",
708 	       (gd->ram_size == 0x20000000) ? "512" : "256", it);
709 	return 0;
710 }
711 
712 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
713 int ft_board_setup(void *blob, bd_t *bd)
714 {
715 	return ft_common_board_setup(blob, bd);
716 }
717 #endif
718 
719 #ifdef CONFIG_CMD_BMODE
720 static const struct boot_mode board_boot_modes[] = {
721 	{"mmc",	MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
722 	{NULL,	0},
723 };
724 #endif
725 
726 int misc_init_r(void)
727 {
728 #ifdef CONFIG_CMD_BMODE
729 	add_board_boot_modes(board_boot_modes);
730 #endif
731 	return 0;
732 }
733 
734 #ifdef CONFIG_LDO_BYPASS_CHECK
735 /* TODO, use external pmic, for now always ldo_enable */
736 void ldo_mode_set(int ldo_bypass)
737 {
738 	return;
739 }
740 #endif
741 
742 #ifdef CONFIG_SPL_BUILD
743 #include <spl.h>
744 #include <libfdt.h>
745 #include "asm/arch/mx6dl-ddr.h"
746 #include "asm/arch/iomux.h"
747 #include "asm/arch/crm_regs.h"
748 
749 static int mx6s_dcd_table[] = {
750 /* ddr-setup.cfg */
751 
752 MX6_IOM_DRAM_SDQS0, 0x00000030,
753 MX6_IOM_DRAM_SDQS1, 0x00000030,
754 MX6_IOM_DRAM_SDQS2, 0x00000030,
755 MX6_IOM_DRAM_SDQS3, 0x00000030,
756 MX6_IOM_DRAM_SDQS4, 0x00000030,
757 MX6_IOM_DRAM_SDQS5, 0x00000030,
758 MX6_IOM_DRAM_SDQS6, 0x00000030,
759 MX6_IOM_DRAM_SDQS7, 0x00000030,
760 
761 MX6_IOM_GRP_B0DS, 0x00000030,
762 MX6_IOM_GRP_B1DS, 0x00000030,
763 MX6_IOM_GRP_B2DS, 0x00000030,
764 MX6_IOM_GRP_B3DS, 0x00000030,
765 MX6_IOM_GRP_B4DS, 0x00000030,
766 MX6_IOM_GRP_B5DS, 0x00000030,
767 MX6_IOM_GRP_B6DS, 0x00000030,
768 MX6_IOM_GRP_B7DS, 0x00000030,
769 MX6_IOM_GRP_ADDDS, 0x00000030,
770 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
771 MX6_IOM_GRP_CTLDS, 0x00000030,
772 
773 MX6_IOM_DRAM_DQM0, 0x00020030,
774 MX6_IOM_DRAM_DQM1, 0x00020030,
775 MX6_IOM_DRAM_DQM2, 0x00020030,
776 MX6_IOM_DRAM_DQM3, 0x00020030,
777 MX6_IOM_DRAM_DQM4, 0x00020030,
778 MX6_IOM_DRAM_DQM5, 0x00020030,
779 MX6_IOM_DRAM_DQM6, 0x00020030,
780 MX6_IOM_DRAM_DQM7, 0x00020030,
781 
782 MX6_IOM_DRAM_CAS, 0x00020030,
783 MX6_IOM_DRAM_RAS, 0x00020030,
784 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
785 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
786 
787 MX6_IOM_DRAM_RESET, 0x00020030,
788 MX6_IOM_DRAM_SDCKE0, 0x00003000,
789 MX6_IOM_DRAM_SDCKE1, 0x00003000,
790 
791 MX6_IOM_DRAM_SDODT0, 0x00003030,
792 MX6_IOM_DRAM_SDODT1, 0x00003030,
793 
794 /* (differential input) */
795 MX6_IOM_DDRMODE_CTL, 0x00020000,
796 /* (differential input) */
797 MX6_IOM_GRP_DDRMODE, 0x00020000,
798 /* disable ddr pullups */
799 MX6_IOM_GRP_DDRPKE, 0x00000000,
800 MX6_IOM_DRAM_SDBA2, 0x00000000,
801 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
802 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
803 
804 /* Read data DQ Byte0-3 delay */
805 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
806 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
807 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
808 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
809 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
810 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
811 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
812 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
813 
814 /*
815  * MDMISC	mirroring	interleaved (row/bank/col)
816  */
817 /* TODO: check what the RALAT field does */
818 MX6_MMDC_P0_MDMISC, 0x00081740,
819 
820 /*
821  * MDSCR	con_req
822  */
823 MX6_MMDC_P0_MDSCR, 0x00008000,
824 
825 
826 /* 800mhz_2x64mx16.cfg */
827 
828 MX6_MMDC_P0_MDPDC, 0x0002002D,
829 MX6_MMDC_P0_MDCFG0, 0x2C305503,
830 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
831 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
832 MX6_MMDC_P0_MDRWD, 0x000026D2,
833 MX6_MMDC_P0_MDOR, 0x00301023,
834 MX6_MMDC_P0_MDOTC, 0x00333030,
835 MX6_MMDC_P0_MDPDC, 0x0002556D,
836 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
837 MX6_MMDC_P0_MDASP, 0x00000017,
838 /* DDR3 DATA BUS SIZE: 64BIT */
839 /* MX6_MMDC_P0_MDCTL, 0x821A0000, */
840 /* DDR3 DATA BUS SIZE: 32BIT */
841 MX6_MMDC_P0_MDCTL, 0x82190000,
842 
843 /* Write commands to DDR */
844 /* Load Mode Registers */
845 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
846 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
847 MX6_MMDC_P0_MDSCR, 0x04008032,
848 MX6_MMDC_P0_MDSCR, 0x00008033,
849 MX6_MMDC_P0_MDSCR, 0x00048031,
850 MX6_MMDC_P0_MDSCR, 0x13208030,
851 /* ZQ calibration */
852 MX6_MMDC_P0_MDSCR, 0x04008040,
853 
854 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
855 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
856 MX6_MMDC_P0_MDREF, 0x00005800,
857 
858 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
859 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
860 
861 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
862 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
863 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
864 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
865 
866 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
867 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
868 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
869 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
870 
871 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
872 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
873 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
874 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
875 
876 MX6_MMDC_P0_MPMUR0, 0x00000800,
877 MX6_MMDC_P1_MPMUR0, 0x00000800,
878 MX6_MMDC_P0_MDSCR, 0x00000000,
879 MX6_MMDC_P0_MAPSR, 0x00011006,
880 };
881 
882 static int mx6dl_dcd_table[] = {
883 /* ddr-setup.cfg */
884 
885 MX6_IOM_DRAM_SDQS0, 0x00000030,
886 MX6_IOM_DRAM_SDQS1, 0x00000030,
887 MX6_IOM_DRAM_SDQS2, 0x00000030,
888 MX6_IOM_DRAM_SDQS3, 0x00000030,
889 MX6_IOM_DRAM_SDQS4, 0x00000030,
890 MX6_IOM_DRAM_SDQS5, 0x00000030,
891 MX6_IOM_DRAM_SDQS6, 0x00000030,
892 MX6_IOM_DRAM_SDQS7, 0x00000030,
893 
894 MX6_IOM_GRP_B0DS, 0x00000030,
895 MX6_IOM_GRP_B1DS, 0x00000030,
896 MX6_IOM_GRP_B2DS, 0x00000030,
897 MX6_IOM_GRP_B3DS, 0x00000030,
898 MX6_IOM_GRP_B4DS, 0x00000030,
899 MX6_IOM_GRP_B5DS, 0x00000030,
900 MX6_IOM_GRP_B6DS, 0x00000030,
901 MX6_IOM_GRP_B7DS, 0x00000030,
902 MX6_IOM_GRP_ADDDS, 0x00000030,
903 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
904 MX6_IOM_GRP_CTLDS, 0x00000030,
905 
906 MX6_IOM_DRAM_DQM0, 0x00020030,
907 MX6_IOM_DRAM_DQM1, 0x00020030,
908 MX6_IOM_DRAM_DQM2, 0x00020030,
909 MX6_IOM_DRAM_DQM3, 0x00020030,
910 MX6_IOM_DRAM_DQM4, 0x00020030,
911 MX6_IOM_DRAM_DQM5, 0x00020030,
912 MX6_IOM_DRAM_DQM6, 0x00020030,
913 MX6_IOM_DRAM_DQM7, 0x00020030,
914 
915 MX6_IOM_DRAM_CAS, 0x00020030,
916 MX6_IOM_DRAM_RAS, 0x00020030,
917 MX6_IOM_DRAM_SDCLK_0, 0x00020030,
918 MX6_IOM_DRAM_SDCLK_1, 0x00020030,
919 
920 MX6_IOM_DRAM_RESET, 0x00020030,
921 MX6_IOM_DRAM_SDCKE0, 0x00003000,
922 MX6_IOM_DRAM_SDCKE1, 0x00003000,
923 
924 MX6_IOM_DRAM_SDODT0, 0x00003030,
925 MX6_IOM_DRAM_SDODT1, 0x00003030,
926 
927 /* (differential input) */
928 MX6_IOM_DDRMODE_CTL, 0x00020000,
929 /* (differential input) */
930 MX6_IOM_GRP_DDRMODE, 0x00020000,
931 /* disable ddr pullups */
932 MX6_IOM_GRP_DDRPKE, 0x00000000,
933 MX6_IOM_DRAM_SDBA2, 0x00000000,
934 /* 40 Ohm drive strength for cs0/1,sdba2,cke0/1,sdwe */
935 MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
936 
937 /* Read data DQ Byte0-3 delay */
938 MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
939 MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
940 MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
941 MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
942 MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333,
943 MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333,
944 MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333,
945 MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333,
946 
947 /*
948  * MDMISC	mirroring	interleaved (row/bank/col)
949  */
950 /* TODO: check what the RALAT field does */
951 MX6_MMDC_P0_MDMISC, 0x00081740,
952 
953 /*
954  * MDSCR	con_req
955  */
956 MX6_MMDC_P0_MDSCR, 0x00008000,
957 
958 
959 /* 800mhz_2x64mx16.cfg */
960 
961 MX6_MMDC_P0_MDPDC, 0x0002002D,
962 MX6_MMDC_P0_MDCFG0, 0x2C305503,
963 MX6_MMDC_P0_MDCFG1, 0xB66D8D63,
964 MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
965 MX6_MMDC_P0_MDRWD, 0x000026D2,
966 MX6_MMDC_P0_MDOR, 0x00301023,
967 MX6_MMDC_P0_MDOTC, 0x00333030,
968 MX6_MMDC_P0_MDPDC, 0x0002556D,
969 /* CS0 End: 7MSB of ((0x10000000, + 512M) -1) >> 25 */
970 MX6_MMDC_P0_MDASP, 0x00000017,
971 /* DDR3 DATA BUS SIZE: 64BIT */
972 MX6_MMDC_P0_MDCTL, 0x821A0000,
973 /* DDR3 DATA BUS SIZE: 32BIT */
974 /* MX6_MMDC_P0_MDCTL, 0x82190000, */
975 
976 /* Write commands to DDR */
977 /* Load Mode Registers */
978 /* TODO Use Auto Self-Refresh mode (Extended Temperature)*/
979 /* MX6_MMDC_P0_MDSCR, 0x04408032, */
980 MX6_MMDC_P0_MDSCR, 0x04008032,
981 MX6_MMDC_P0_MDSCR, 0x00008033,
982 MX6_MMDC_P0_MDSCR, 0x00048031,
983 MX6_MMDC_P0_MDSCR, 0x13208030,
984 /* ZQ calibration */
985 MX6_MMDC_P0_MDSCR, 0x04008040,
986 
987 MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
988 MX6_MMDC_P1_MPZQHWCTRL, 0xA1390003,
989 MX6_MMDC_P0_MDREF, 0x00005800,
990 
991 MX6_MMDC_P0_MPODTCTRL, 0x00000000,
992 MX6_MMDC_P1_MPODTCTRL, 0x00000000,
993 
994 MX6_MMDC_P0_MPDGCTRL0, 0x42360232,
995 MX6_MMDC_P0_MPDGCTRL1, 0x021F022A,
996 MX6_MMDC_P1_MPDGCTRL0, 0x421E0224,
997 MX6_MMDC_P1_MPDGCTRL1, 0x02110218,
998 
999 MX6_MMDC_P0_MPRDDLCTL, 0x41434344,
1000 MX6_MMDC_P1_MPRDDLCTL, 0x4345423E,
1001 MX6_MMDC_P0_MPWRDLCTL, 0x39383339,
1002 MX6_MMDC_P1_MPWRDLCTL, 0x3E363930,
1003 
1004 MX6_MMDC_P0_MPWLDECTRL0, 0x00340039,
1005 MX6_MMDC_P0_MPWLDECTRL1, 0x002C002D,
1006 MX6_MMDC_P1_MPWLDECTRL0, 0x00120019,
1007 MX6_MMDC_P1_MPWLDECTRL1, 0x0012002D,
1008 
1009 MX6_MMDC_P0_MPMUR0, 0x00000800,
1010 MX6_MMDC_P1_MPMUR0, 0x00000800,
1011 MX6_MMDC_P0_MDSCR, 0x00000000,
1012 MX6_MMDC_P0_MAPSR, 0x00011006,
1013 };
1014 
1015 static void ccgr_init(void)
1016 {
1017 	struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
1018 
1019 	writel(0x00C03F3F, &ccm->CCGR0);
1020 	writel(0x0030FC03, &ccm->CCGR1);
1021 	writel(0x0FFFFFF3, &ccm->CCGR2);
1022 	writel(0x3FF0300F, &ccm->CCGR3);
1023 	writel(0x00FFF300, &ccm->CCGR4);
1024 	writel(0x0F0000F3, &ccm->CCGR5);
1025 	writel(0x000003FF, &ccm->CCGR6);
1026 
1027 /*
1028  * Setup CCM_CCOSR register as follows:
1029  *
1030  * cko1_en  = 1	   --> CKO1 enabled
1031  * cko1_div = 111  --> divide by 8
1032  * cko1_sel = 1011 --> ahb_clk_root
1033  *
1034  * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
1035  */
1036 	writel(0x000000FB, &ccm->ccosr);
1037 }
1038 
1039 static void ddr_init(int *table, int size)
1040 {
1041 	int i;
1042 
1043 	for (i = 0; i < size / 2 ; i++)
1044 		writel(table[2 * i + 1], table[2 * i]);
1045 }
1046 
1047 static void spl_dram_init(void)
1048 {
1049 	int minc, maxc;
1050 
1051 	switch (get_cpu_temp_grade(&minc, &maxc)) {
1052 	case TEMP_COMMERCIAL:
1053 	case TEMP_EXTCOMMERCIAL:
1054 		if (is_cpu_type(MXC_CPU_MX6DL)) {
1055 			puts("Commercial temperature grade DDR3 timings, 64bit bus width.\n");
1056 			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1057 		} else {
1058 			puts("Commercial temperature grade DDR3 timings, 32bit bus width.\n");
1059 			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1060 		}
1061 		break;
1062 	case TEMP_INDUSTRIAL:
1063 	case TEMP_AUTOMOTIVE:
1064 	default:
1065 		if (is_cpu_type(MXC_CPU_MX6DL)) {
1066 			ddr_init(mx6dl_dcd_table, ARRAY_SIZE(mx6dl_dcd_table));
1067 		} else {
1068 			puts("Industrial temperature grade DDR3 timings, 32bit bus width.\n");
1069 			ddr_init(mx6s_dcd_table, ARRAY_SIZE(mx6s_dcd_table));
1070 		}
1071 		break;
1072 	};
1073 	udelay(100);
1074 }
1075 
1076 void board_init_f(ulong dummy)
1077 {
1078 	/* setup AIPS and disable watchdog */
1079 	arch_cpu_init();
1080 
1081 	ccgr_init();
1082 	gpr_init();
1083 
1084 	/* iomux and setup of i2c */
1085 	board_early_init_f();
1086 
1087 	/* setup GP timer */
1088 	timer_init();
1089 
1090 	/* UART clocks enabled and gd valid - init serial console */
1091 	preloader_console_init();
1092 
1093 	/* Make sure we use dte mode */
1094 	setup_dtemode_uart();
1095 
1096 	/* DDR initialization */
1097 	spl_dram_init();
1098 
1099 	/* Clear the BSS. */
1100 	memset(__bss_start, 0, __bss_end - __bss_start);
1101 
1102 	/* load/boot image from boot device */
1103 	board_init_r(NULL, 0);
1104 }
1105 
1106 void reset_cpu(ulong addr)
1107 {
1108 }
1109 
1110 #endif
1111 
1112 static struct mxc_serial_platdata mxc_serial_plat = {
1113 	.reg = (struct mxc_uart *)UART1_BASE,
1114 	.use_dte = true,
1115 };
1116 
1117 U_BOOT_DEVICE(mxc_serial) = {
1118 	.name = "serial_mxc",
1119 	.platdata = &mxc_serial_plat,
1120 };
1121