1/*
2 * Copyright (C) 2013 Boundary Devices
3 * Copyright (C) 2014-2016, Toradex AG
4 *
5 * SPDX-License-Identifier:	GPL-2.0+
6 *
7 * Device Configuration Data (DCD)
8 *
9 * Each entry must have the format:
10 * Addr-type           Address        Value
11 *
12 * where:
13 *      Addr-type register length (1,2 or 4 bytes)
14 *      Address   absolute address of the register
15 *      value     value to be stored in the register
16 */
17
18/* set the default clock gate to save power */
19DATA 4, CCM_CCGR0, 0x00C03F3F
20DATA 4, CCM_CCGR1, 0x0030FC03
21DATA 4, CCM_CCGR2, 0x0FFFC000
22DATA 4, CCM_CCGR3, 0x3FF00000
23DATA 4, CCM_CCGR4, 0x00FFF300
24DATA 4, CCM_CCGR5, 0x0F0000C3
25DATA 4, CCM_CCGR6, 0x000003FF
26
27/* enable AXI cache for VDOA/VPU/IPU */
28DATA 4, MX6_IOMUXC_GPR4, 0xF00000CF
29/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
30DATA 4, MX6_IOMUXC_GPR6, 0x007F007F
31DATA 4, MX6_IOMUXC_GPR7, 0x007F007F
32
33/*
34 * Setup CCM_CCOSR register as follows:
35 *
36 * cko1_en  = 1	   --> CKO1 enabled
37 * cko1_div = 111  --> divide by 8
38 * cko1_sel = 1011 --> ahb_clk_root
39 *
40 * This sets CKO1 at ahb_clk_root/8 = 132/8 = 16.5 MHz
41 */
42DATA 4, CCM_CCOSR, 0x000000fb
43