1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 Toradex AG 4 */ 5 #include <common.h> 6 #include <asm/arch/clock.h> 7 #include <asm/arch/crm_regs.h> 8 #include <asm/arch/imx-regs.h> 9 #include <asm/arch-mx6/clock.h> 10 #include <asm/arch-mx6/imx-regs.h> 11 #include <asm/arch-mx6/mx6ull_pins.h> 12 #include <asm/arch/sys_proto.h> 13 #include <asm/gpio.h> 14 #include <asm/mach-imx/boot_mode.h> 15 #include <asm/mach-imx/iomux-v3.h> 16 #include <asm/io.h> 17 #include <common.h> 18 #include <dm.h> 19 #include <dm/platform_data/serial_mxc.h> 20 #include <fdt_support.h> 21 #include <fsl_esdhc.h> 22 #include <imx_thermal.h> 23 #include <jffs2/load_kernel.h> 24 #include <linux/sizes.h> 25 #include <mmc.h> 26 #include <miiphy.h> 27 #include <mtd_node.h> 28 #include <netdev.h> 29 #include <usb.h> 30 #include <usb/ehci-ci.h> 31 #include "../common/tdx-common.h" 32 33 DECLARE_GLOBAL_DATA_PTR; 34 35 #define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 36 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ 37 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 38 39 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ 40 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ 41 PAD_CTL_SRE_FAST | PAD_CTL_HYS) 42 43 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ 44 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) 45 #define ENET_PAD_CTRL_MII (PAD_CTL_DSE_40ohm) 46 47 #define ENET_RX_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_DSE_48ohm) 48 49 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_PUS_100K_UP | \ 50 PAD_CTL_DSE_48ohm) 51 52 #define NAND_PAD_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_SRE_SLOW | PAD_CTL_HYS) 53 54 #define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_48ohm | PAD_CTL_PUS_22K_UP) 55 56 #define USB_CDET_GPIO IMX_GPIO_NR(7, 14) 57 58 int dram_init(void) 59 { 60 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); 61 62 return 0; 63 } 64 65 static iomux_v3_cfg_t const uart1_pads[] = { 66 MX6_PAD_UART1_TX_DATA__UART1_DTE_RX | MUX_PAD_CTRL(UART_PAD_CTRL), 67 MX6_PAD_UART1_RX_DATA__UART1_DTE_TX | MUX_PAD_CTRL(UART_PAD_CTRL), 68 MX6_PAD_UART1_RTS_B__UART1_DTE_CTS | MUX_PAD_CTRL(UART_PAD_CTRL), 69 MX6_PAD_UART1_CTS_B__UART1_DTE_RTS | MUX_PAD_CTRL(UART_PAD_CTRL), 70 }; 71 72 #ifdef CONFIG_FSL_ESDHC 73 static iomux_v3_cfg_t const usdhc1_pads[] = { 74 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), 75 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), 76 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 77 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 78 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 79 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), 80 81 MX6_PAD_SNVS_TAMPER0__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), 82 }; 83 #endif 84 85 static iomux_v3_cfg_t const usb_cdet_pads[] = { 86 MX6_PAD_SNVS_TAMPER2__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), 87 }; 88 89 #ifdef CONFIG_NAND_MXS 90 static iomux_v3_cfg_t const gpmi_pads[] = { 91 MX6_PAD_NAND_DATA00__RAWNAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL), 92 MX6_PAD_NAND_DATA01__RAWNAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL), 93 MX6_PAD_NAND_DATA02__RAWNAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL), 94 MX6_PAD_NAND_DATA03__RAWNAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL), 95 MX6_PAD_NAND_DATA04__RAWNAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL), 96 MX6_PAD_NAND_DATA05__RAWNAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL), 97 MX6_PAD_NAND_DATA06__RAWNAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL), 98 MX6_PAD_NAND_DATA07__RAWNAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL), 99 MX6_PAD_NAND_CLE__RAWNAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL), 100 MX6_PAD_NAND_ALE__RAWNAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL), 101 MX6_PAD_NAND_RE_B__RAWNAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 102 MX6_PAD_NAND_WE_B__RAWNAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 103 MX6_PAD_NAND_CE0_B__RAWNAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL), 104 MX6_PAD_NAND_READY_B__RAWNAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL), 105 }; 106 107 static void setup_gpmi_nand(void) 108 { 109 imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); 110 111 setup_gpmi_io_clk((3 << MXC_CCM_CSCDR1_BCH_PODF_OFFSET) | 112 (3 << MXC_CCM_CSCDR1_GPMI_PODF_OFFSET)); 113 } 114 #endif 115 116 #ifdef CONFIG_VIDEO_MXS 117 static iomux_v3_cfg_t const lcd_pads[] = { 118 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 119 MX6_PAD_LCD_ENABLE__LCDIF_ENABLE | MUX_PAD_CTRL(LCD_PAD_CTRL), 120 MX6_PAD_LCD_HSYNC__LCDIF_HSYNC | MUX_PAD_CTRL(LCD_PAD_CTRL), 121 MX6_PAD_LCD_CLK__LCDIF_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL), 122 MX6_PAD_LCD_DATA00__LCDIF_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL), 123 MX6_PAD_LCD_DATA01__LCDIF_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL), 124 MX6_PAD_LCD_DATA02__LCDIF_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL), 125 MX6_PAD_LCD_DATA03__LCDIF_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL), 126 MX6_PAD_LCD_DATA04__LCDIF_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL), 127 MX6_PAD_LCD_DATA05__LCDIF_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL), 128 MX6_PAD_LCD_DATA06__LCDIF_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL), 129 MX6_PAD_LCD_DATA07__LCDIF_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL), 130 MX6_PAD_LCD_DATA08__LCDIF_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL), 131 MX6_PAD_LCD_DATA09__LCDIF_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL), 132 MX6_PAD_LCD_DATA10__LCDIF_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL), 133 MX6_PAD_LCD_DATA11__LCDIF_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL), 134 MX6_PAD_LCD_DATA12__LCDIF_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL), 135 MX6_PAD_LCD_DATA13__LCDIF_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL), 136 MX6_PAD_LCD_DATA14__LCDIF_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL), 137 MX6_PAD_LCD_DATA15__LCDIF_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL), 138 MX6_PAD_LCD_DATA16__LCDIF_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL), 139 MX6_PAD_LCD_DATA17__LCDIF_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL), 140 }; 141 142 static iomux_v3_cfg_t const backlight_pads[] = { 143 /* Backlight On */ 144 MX6_PAD_JTAG_TMS__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 145 /* Backlight PWM<A> (multiplexed pin) */ 146 MX6_PAD_NAND_WP_B__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), 147 }; 148 149 #define GPIO_BL_ON IMX_GPIO_NR(1, 11) 150 #define GPIO_PWM_A IMX_GPIO_NR(4, 11) 151 152 static int setup_lcd(void) 153 { 154 imx_iomux_v3_setup_multiple_pads(lcd_pads, ARRAY_SIZE(lcd_pads)); 155 156 imx_iomux_v3_setup_multiple_pads(backlight_pads, ARRAY_SIZE(backlight_pads)); 157 158 /* Set BL_ON */ 159 gpio_request(GPIO_BL_ON, "BL_ON"); 160 gpio_direction_output(GPIO_BL_ON, 1); 161 162 /* Set PWM<A> to full brightness (assuming inversed polarity) */ 163 gpio_request(GPIO_PWM_A, "PWM<A>"); 164 gpio_direction_output(GPIO_PWM_A, 0); 165 166 return 0; 167 } 168 #endif 169 170 #ifdef CONFIG_FEC_MXC 171 static iomux_v3_cfg_t const fec2_pads[] = { 172 MX6_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 | MUX_PAD_CTRL(ENET_PAD_CTRL) | MUX_MODE_SION, 173 MX6_PAD_GPIO1_IO06__ENET2_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 174 MX6_PAD_GPIO1_IO07__ENET2_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL_MII), 175 MX6_PAD_ENET2_RX_DATA0__ENET2_RDATA00 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 176 MX6_PAD_ENET2_RX_DATA1__ENET2_RDATA01 | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 177 MX6_PAD_ENET2_RX_ER__ENET2_RX_ER | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 178 MX6_PAD_ENET2_RX_EN__ENET2_RX_EN | MUX_PAD_CTRL(ENET_RX_PAD_CTRL), 179 MX6_PAD_ENET2_TX_DATA0__ENET2_TDATA00 | MUX_PAD_CTRL(ENET_PAD_CTRL), 180 MX6_PAD_ENET2_TX_DATA1__ENET2_TDATA01 | MUX_PAD_CTRL(ENET_PAD_CTRL), 181 MX6_PAD_ENET2_TX_EN__ENET2_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), 182 }; 183 184 static void setup_iomux_fec(void) 185 { 186 imx_iomux_v3_setup_multiple_pads(fec2_pads, ARRAY_SIZE(fec2_pads)); 187 } 188 #endif 189 190 static void setup_iomux_uart(void) 191 { 192 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); 193 } 194 195 #ifdef CONFIG_FSL_ESDHC 196 197 #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 0) 198 199 static struct fsl_esdhc_cfg usdhc_cfg[] = { 200 {USDHC1_BASE_ADDR, 0, 4}, 201 }; 202 203 int board_mmc_getcd(struct mmc *mmc) 204 { 205 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; 206 int ret = 0; 207 208 switch (cfg->esdhc_base) { 209 case USDHC1_BASE_ADDR: 210 ret = !gpio_get_value(USDHC1_CD_GPIO); 211 break; 212 } 213 214 return ret; 215 } 216 217 int board_mmc_init(bd_t *bis) 218 { 219 int i, ret; 220 221 /* USDHC1 is mmc0 */ 222 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { 223 switch (i) { 224 case 0: 225 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, 226 ARRAY_SIZE(usdhc1_pads)); 227 gpio_request(USDHC1_CD_GPIO, "usdhc1_cd"); 228 gpio_direction_input(USDHC1_CD_GPIO); 229 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); 230 break; 231 default: 232 printf("Warning: you configured more USDHC controllers" 233 "(%d) than supported by the board\n", i + 1); 234 return -EINVAL; 235 } 236 237 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); 238 if (ret) 239 return ret; 240 } 241 242 return 0; 243 } 244 #endif 245 246 #ifdef CONFIG_FEC_MXC 247 248 static int setup_fec(void) 249 { 250 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 251 int ret; 252 253 setup_iomux_fec(); 254 255 /* provide the PHY clock from the i.MX 6 */ 256 ret = enable_fec_anatop_clock(1, ENET_50MHZ); 257 if (ret) 258 return ret; 259 260 /* Use 50M anatop REF_CLK and output it on the ENET2_TX_CLK */ 261 clrsetbits_le32(&iomuxc_regs->gpr[1], 262 IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK, 263 IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK); 264 265 return 0; 266 } 267 268 int board_phy_config(struct phy_device *phydev) 269 { 270 if (phydev->drv->config) 271 phydev->drv->config(phydev); 272 return 0; 273 } 274 #endif 275 276 int board_early_init_f(void) 277 { 278 setup_iomux_uart(); 279 280 return 0; 281 } 282 283 int board_init(void) 284 { 285 /* address of boot parameters */ 286 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 287 288 #ifdef CONFIG_FEC_MXC 289 setup_fec(); 290 #endif 291 292 #ifdef CONFIG_NAND_MXS 293 setup_gpmi_nand(); 294 #endif 295 296 #ifdef CONFIG_VIDEO_MXS 297 setup_lcd(); 298 #endif 299 300 #ifdef CONFIG_USB_EHCI_MX6 301 imx_iomux_v3_setup_multiple_pads(usb_cdet_pads, ARRAY_SIZE(usb_cdet_pads)); 302 gpio_request(USB_CDET_GPIO, "usb-cdet-gpio"); 303 #endif 304 305 return 0; 306 } 307 308 #ifdef CONFIG_CMD_BMODE 309 /* TODO */ 310 static const struct boot_mode board_boot_modes[] = { 311 /* 4 bit bus width */ 312 {"nand", MAKE_CFGVAL(0x40, 0x34, 0x00, 0x00)}, 313 {"sd1", MAKE_CFGVAL(0x10, 0x10, 0x00, 0x00)}, 314 {NULL, 0}, 315 }; 316 #endif 317 318 int board_late_init(void) 319 { 320 int minc, maxc; 321 322 if (get_cpu_temp_grade(&minc, &maxc) != TEMP_COMMERCIAL) 323 env_set("variant", "-wifi"); 324 325 #ifdef CONFIG_CMD_BMODE 326 add_board_boot_modes(board_boot_modes); 327 #endif 328 329 #ifdef CONFIG_CMD_USB_SDP 330 if (is_boot_from_usb()) { 331 printf("Serial Downloader recovery mode, using sdp command\n"); 332 env_set("bootdelay", "0"); 333 env_set("bootcmd", "sdp 0"); 334 } 335 #endif /* CONFIG_CMD_USB_SDP */ 336 337 return 0; 338 } 339 340 int checkboard(void) 341 { 342 printf("Model: Toradex Colibri iMX6ULL\n"); 343 344 return 0; 345 } 346 347 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) 348 int ft_board_setup(void *blob, bd_t *bd) 349 { 350 #if defined(CONFIG_FDT_FIXUP_PARTITIONS) 351 static struct node_info nodes[] = { 352 { "fsl,imx6ull-gpmi-nand", MTD_DEV_TYPE_NAND, }, 353 { "fsl,imx6q-gpmi-nand", MTD_DEV_TYPE_NAND, }, 354 }; 355 356 /* Update partition nodes using info from mtdparts env var */ 357 puts(" Updating MTD partitions...\n"); 358 fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes)); 359 #endif 360 361 return ft_common_board_setup(blob, bd); 362 } 363 #endif 364 365 #ifdef CONFIG_USB_EHCI_MX6 366 static iomux_v3_cfg_t const usb_otg2_pads[] = { 367 MX6_PAD_GPIO1_IO02__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), 368 }; 369 370 int board_ehci_hcd_init(int port) 371 { 372 switch (port) { 373 case 0: 374 break; 375 case 1: 376 imx_iomux_v3_setup_multiple_pads(usb_otg2_pads, 377 ARRAY_SIZE(usb_otg2_pads)); 378 break; 379 default: 380 return -EINVAL; 381 } 382 return 0; 383 } 384 385 int board_usb_phy_mode(int port) 386 { 387 switch (port) { 388 case 0: 389 if (gpio_get_value(USB_CDET_GPIO)) 390 return USB_INIT_DEVICE; 391 else 392 return USB_INIT_HOST; 393 case 1: 394 default: 395 return USB_INIT_HOST; 396 } 397 } 398 #endif 399 400 static struct mxc_serial_platdata mxc_serial_plat = { 401 .reg = (struct mxc_uart *)UART1_BASE, 402 .use_dte = 1, 403 }; 404 405 U_BOOT_DEVICE(mxc_serial) = { 406 .name = "serial_mxc", 407 .platdata = &mxc_serial_plat, 408 }; 409