1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2014-2016, Toradex AG
4 */
5
6// Register Output for PF0100 programmer
7// Customer: Toradex AG
8// Program: Apalis iMX6
9// Sample marking:
10// Date: 12.02.2014
11// Time: 17:16:41
12// Generated from Spreadsheet Revision: P1.8
13
14/* sed commands to get from programmer script to struct */
15/* sed -e 's/^WRITE_I2C:\(..\):\(..\)/\{pmic_i2c, 0x\1, 0x\2\},/g' -e 's/^DELAY:\([0-9]*\)/\{pmic_delay, 0, \1\},/g' pf0100_otp.txt > pf0100_otp.inc
16   sed -i -e 's/^VPGM:ON/\{pmic_vpgm, 0, 1},/g' -e 's/^VPGM:OFF/\{pmic_vpgm, 0, 0},/g' pf0100_otp.inc
17   sed -i -e 's/^PWRON: HIGH/\{pmic_pwr, 0, 1},/g' -e 's/^PWRON:LOW/\{pmic_pwr, 0, 0},/g' pf0100_otp.inc */
18
19enum { pmic_i2c, pmic_delay, pmic_vpgm, pmic_pwr };
20struct pmic_otp_prog_t{
21	unsigned char cmd;
22	unsigned char reg;
23	unsigned short value;
24};
25
26struct pmic_otp_prog_t pmic_otp_prog[] = {
27{pmic_i2c, 0x7F, 0x01}, // Access FSL EXT Page 1
28{pmic_i2c, 0xA0, 0x2B}, // Auto gen from Row94
29{pmic_i2c, 0xA1, 0x01}, // Auto gen from Row95
30{pmic_i2c, 0xA2, 0x05}, // Auto gen from Row96
31{pmic_i2c, 0xA8, 0x2B}, // Auto gen from Row102
32{pmic_i2c, 0xA9, 0x02}, // Auto gen from Row103
33{pmic_i2c, 0xAA, 0x01}, // Auto gen from Row104
34{pmic_i2c, 0xAC, 0x18}, // Auto gen from Row106
35{pmic_i2c, 0xAE, 0x01}, // Auto gen from Row108
36{pmic_i2c, 0xB0, 0x2C}, // Auto gen from Row110
37{pmic_i2c, 0xB1, 0x04}, // Auto gen from Row111
38{pmic_i2c, 0xB2, 0x01}, // Auto gen from Row112
39{pmic_i2c, 0xB4, 0x2C}, // Auto gen from Row114
40{pmic_i2c, 0xB5, 0x04}, // Auto gen from Row115
41{pmic_i2c, 0xB6, 0x01}, // Auto gen from Row116
42{pmic_i2c, 0xB8, 0x18}, // Auto gen from Row118
43{pmic_i2c, 0xBA, 0x01}, // Auto gen from Row120
44{pmic_i2c, 0xBD, 0x1F}, // Auto gen from Row123
45{pmic_i2c, 0xC0, 0x06}, // Auto gen from Row126
46{pmic_i2c, 0xC4, 0x04}, // Auto gen from Row130
47{pmic_i2c, 0xC8, 0x0E}, // Auto gen from Row134
48{pmic_i2c, 0xC9, 0x08}, // Auto gen from Row135
49{pmic_i2c, 0xCC, 0x0E}, // Auto gen from Row138
50{pmic_i2c, 0xCD, 0x05}, // Auto gen from Row139
51{pmic_i2c, 0xD0, 0x0C}, // Auto gen from Row142
52{pmic_i2c, 0xD1, 0x05}, // Auto gen from Row143
53{pmic_i2c, 0xD5, 0x07}, // Auto gen from Row147
54{pmic_i2c, 0xD8, 0x07}, // Auto gen from Row150
55{pmic_i2c, 0xD9, 0x06}, // Auto gen from Row151
56{pmic_i2c, 0xDC, 0x0A}, // Auto gen from Row154
57{pmic_i2c, 0xDD, 0x03}, // Auto gen from Row155
58{pmic_i2c, 0xE0, 0x07}, // Auto gen from Row158
59
60#if 0 /* TBB mode */
61{pmic_i2c, 0xE4, 0x80}, // TBB_POR = 1
62{pmic_delay, 0, 10},
63#else
64// Write OTP
65{pmic_i2c, 0xE4, 0x02}, // FUSE POR1=1
66{pmic_i2c, 0xE5, 0x02}, // FUSE POR2=1
67{pmic_i2c, 0xE6, 0x02}, // FUSE POR3=1
68{pmic_i2c, 0xF0, 0x1F}, // Enable ECC for fuse banks 1 to 5 by writing to OTP EN ECC0 register
69{pmic_i2c, 0xF1, 0x1F}, // Enable ECC for fuse banks 6 to 10 by writing to OTP EN ECC1 register
70{pmic_i2c, 0x7F, 0x02}, // Access PF0100 EXT Page2
71{pmic_i2c, 0xD0, 0x1F}, // Set Auto ECC for fuse banks 1 to 5 by writing to OTP AUTO ECC0 register
72{pmic_i2c, 0xD1, 0x1F}, // Set Auto ECC for fuse banks 6 to 10 by writing to OTP AUTO ECC1 register
73//-----------------------------------------------------------------------------------
74{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
75{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
76{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
77{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
78{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
79{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
80{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
81{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
82{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
83{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
84//-----------------------------------------------------------------------------------
85{pmic_vpgm, 0, 1}, // Turn ON 8V SWBST
86//VPGM:DOWN:n
87//VPGM:UP:n
88{pmic_delay, 0, 500}, // Adds 500msec delay to allow VPGM time to ramp up
89//-----------------------------------------------------------------------------------
90// PF0100 OTP MANUAL-PROGRAMMING (BANK 1 thru 10)
91//-----------------------------------------------------------------------------------
92// BANK 1
93//-----------------------------------------------------------------------------------
94{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
95{pmic_i2c, 0xF1, 0x03}, // Set Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
96{pmic_i2c, 0xF1, 0x0B}, // Set Bank 1 ANTIFUSE_EN
97{pmic_delay, 0, 10}, // Allow time for bank programming to complete
98{pmic_i2c, 0xF1, 0x03}, // Reset Bank 1 ANTIFUSE_EN
99{pmic_i2c, 0xF1, 0x00}, // Reset Bank 1 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
100//-----------------------------------------------------------------------------------
101// BANK 2
102//-----------------------------------------------------------------------------------
103{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
104{pmic_i2c, 0xF2, 0x03}, // Set Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
105{pmic_i2c, 0xF2, 0x0B}, // Set Bank 2 ANTIFUSE_EN
106{pmic_delay, 0, 10}, // Allow time for bank programming to complete
107{pmic_i2c, 0xF2, 0x03}, // Reset Bank 2 ANTIFUSE_EN
108{pmic_i2c, 0xF2, 0x00}, // Reset Bank 2 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
109//-----------------------------------------------------------------------------------
110// BANK 3
111//-----------------------------------------------------------------------------------
112{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
113{pmic_i2c, 0xF3, 0x03}, // Set Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
114{pmic_i2c, 0xF3, 0x0B}, // Set Bank 3 ANTIFUSE_EN
115{pmic_delay, 0, 10}, // Allow time for bank programming to complete
116{pmic_i2c, 0xF3, 0x03}, // Reset Bank 3 ANTIFUSE_EN
117{pmic_i2c, 0xF3, 0x00}, // Reset Bank 3 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
118//-----------------------------------------------------------------------------------
119// BANK 4
120//-----------------------------------------------------------------------------------
121{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
122{pmic_i2c, 0xF4, 0x03}, // Set Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
123{pmic_i2c, 0xF4, 0x0B}, // Set Bank 4 ANTIFUSE_EN
124{pmic_delay, 0, 10}, // Allow time for bank programming to complete
125{pmic_i2c, 0xF4, 0x03}, // Reset Bank 4 ANTIFUSE_EN
126{pmic_i2c, 0xF4, 0x00}, // Reset Bank 4 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
127//-----------------------------------------------------------------------------------
128// BANK 5
129//-----------------------------------------------------------------------------------
130{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
131{pmic_i2c, 0xF5, 0x03}, // Set Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
132{pmic_i2c, 0xF5, 0x0B}, // Set Bank 5 ANTIFUSE_EN
133{pmic_delay, 0, 10}, // Allow time for bank programming to complete
134{pmic_i2c, 0xF5, 0x03}, // Reset Bank 5 ANTIFUSE_EN
135{pmic_i2c, 0xF5, 0x00}, // Reset Bank 5 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
136//-----------------------------------------------------------------------------------
137// BANK 6
138//-----------------------------------------------------------------------------------
139{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
140{pmic_i2c, 0xF6, 0x03}, // Set Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
141{pmic_i2c, 0xF6, 0x0B}, // Set Bank 6 ANTIFUSE_EN
142{pmic_delay, 0, 10}, // Allow time for bank programming to complete
143{pmic_i2c, 0xF6, 0x03}, // Reset Bank 6 ANTIFUSE_EN
144{pmic_i2c, 0xF6, 0x00}, // Reset Bank 6 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
145//-----------------------------------------------------------------------------------
146// BANK 7
147//-----------------------------------------------------------------------------------
148{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
149{pmic_i2c, 0xF7, 0x03}, // Set Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
150{pmic_i2c, 0xF7, 0x0B}, // Set Bank 7 ANTIFUSE_EN
151{pmic_delay, 0, 10}, // Allow time for bank programming to complete
152{pmic_i2c, 0xF7, 0x03}, // Reset Bank 7 ANTIFUSE_EN
153{pmic_i2c, 0xF7, 0x00}, // Reset Bank 7 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
154//-----------------------------------------------------------------------------------
155// BANK 8
156//-----------------------------------------------------------------------------------
157{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
158{pmic_i2c, 0xF8, 0x03}, // Set Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
159{pmic_i2c, 0xF8, 0x0B}, // Set Bank 8 ANTIFUSE_EN
160{pmic_delay, 0, 10}, // Allow time for bank programming to complete
161{pmic_i2c, 0xF8, 0x03}, // Reset Bank 8 ANTIFUSE_EN
162{pmic_i2c, 0xF8, 0x00}, // Reset Bank 8 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
163//-----------------------------------------------------------------------------------
164// BANK 9
165//-----------------------------------------------------------------------------------
166{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
167{pmic_i2c, 0xF9, 0x03}, // Set Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
168{pmic_i2c, 0xF9, 0x0B}, // Set Bank 9 ANTIFUSE_EN
169{pmic_delay, 0, 10}, // Allow time for bank programming to complete
170{pmic_i2c, 0xF9, 0x03}, // Reset Bank 9 ANTIFUSE_EN
171{pmic_i2c, 0xF9, 0x00}, // Reset Bank 9 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
172//-----------------------------------------------------------------------------------
173// BANK 10
174//-----------------------------------------------------------------------------------
175{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
176{pmic_i2c, 0xFA, 0x03}, // Set Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
177{pmic_i2c, 0xFA, 0x0B}, // Set Bank 10 ANTIFUSE_EN
178{pmic_delay, 0, 10}, // Allow time for bank programming to complete
179{pmic_i2c, 0xFA, 0x03}, // Reset Bank 10 ANTIFUSE_EN
180{pmic_i2c, 0xFA, 0x00}, // Reset Bank 10 ANTIFUSE_RW and ANTIFUSE_BYPASS bits
181//-----------------------------------------------------------------------------------
182{pmic_vpgm, 0, 0}, // Turn off 8V SWBST
183{pmic_delay, 0, 500}, // Adds delay to allow VPGM to bleed off
184{pmic_i2c, 0xD0, 0x00}, // Clear
185{pmic_i2c, 0xD1, 0x00}, // Clear
186{pmic_pwr, 0, 0}, // PWRON LOW to reload new OTP data
187{pmic_delay, 0, 500},
188{pmic_pwr, 0, 1},
189#endif
190};